XA3S500E-4PQG208I Datasheet, PDF (20/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

R
Configurable Logic Block Timing
Table 20: CLB (SLICEM) Timing
Symbol
Description
Clock-to-Output Times
T_CKO
When reading from the FFX (FFY) Flip-Flop, the time from the active
transition at the CLK input to data appearing at the XQ (YQ) output
Setup Times
T_AS
Time from the setup of data at the F or G input to the active transition
at the CLK input of the CLB
T_DICK
Time from the setup of data at the BX or BY input to the active
transition at the CLK input of the CLB
Hold Times
T_AH
Time from the active transition at the CLK input to the point where
data is last held at the F or G input
T_CKDI
Time from the active transition at the CLK input to the point where
data is last held at the BX or BY input
Clock Timing
T_CH
The High pulse width of the CLB’s CLK signal
T_CL
The Low pulse width of the CLK signal
F_TOG
Toggle frequency (for export control)
Propagation Times
T_ILO
The time it takes for data to travel from the CLB’s F (G) input to the X
(Y) output
Set/Reset Pulse Width
T_{RPW_CLB}
The minimum allowable pulse width, High or Low, to the CLB’s SR
input
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6.
-4 Speed Grade
Min
Max
-
0.60
0.52
-
1.81
-
0
-
0
-
0.80
-
0.80
-
0
572
-
0.76
1.80
-
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
20