XA3S500E-4PQG208I Datasheet, PDF (34/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

R
Byte Peripheral Interface Configuration Timing
Table 42: Timing for BPI Configuration Mode
Symbol
Description
T_CCLK1
T_CCLKn
T_MINIT
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising
edge of INIT_B
T_INITM
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising
edge of INIT_B
T_INITADDR Minimum period of initial A[23:0] address cycle;
LDC[2:0] and HDC are asserted and valid
BPI-UP:
(M[2:0]=<0:1:0>)
BPI-DN:
(M[2:0]=<0:1:1>)
T_CCO
T_DCC
T_CCD
Address A[23:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
Minimum Maximum
(see Table 34)
(see Table 34)
50
-
Units
ns
0
-
ns
5
5
T_CCLK1
cycles
2
2
See Table 38
See Table 38
See Table 38
Table 43: Configuration Timing Requirements for Attached Parallel NOR Flash
Symbol
Description
Requirement
Units
T_CE
(t_ELQV)
Parallel NOR Flash PROM chip-select
time
T_CE ≤ T_INITADDR
ns
T_OE
(t_GLQV)
Parallel NOR Flash PROM
output-enable time
T_OE ≤ T_INITADDR
ns
T_ACC
(t_AVQV)
Parallel NOR Flash PROM read access
time
T_ACC ≤ 0.5T_CCLKn(min) – T_CCO – T_DCC – PCB
ns
T_BYTE
(t_FLQV,
t_FHQV)
For x8/x16 PROMs only: BYTE# to
output valid time⁽³⁾
T_BYTE ≤ T_INITADDR
ns
Notes:
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s HSWAP pin is High or Low.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
34