XA3S500E-4PQG208I Datasheet, PDF (11/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Single-Ended I/O Standards
Table 9: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD
Attribute
V_CCO for Drivers⁽²⁾
Min (V) Nom (V) Max (V)
Min (V)
V_REF
Nom (V)
Max (V)
V_IL
Max (V)
V_IH
Min (V)
LVTTL
3.0
3.3
3.465
0.8
2.0
LVCMOS33⁽⁴⁾
3.0
3.3
3.465
0.8
2.0
LVCMOS25^(4,5)
2.3
2.5
2.7
LVCMOS18
1.65
1.8
1.95
LVCMOS15
1.4
1.5
1.6
V_REF is not used for
these I/O standards
0.7
1.7
0.4
0.8
0.4
0.8
LVCMOS12
1.1
1.2
1.3
0.4
0.7
PCI33_3
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
3.0
3.3
3.465
0.3 * V_CCO
0.5 * V_CCO
1.7
1.8
1.9
0.8
0.9
1.1
V_REF - 0.1
V_REF + 0.1
1.7
1.8
1.9
-
1.1
-
V_REF - 0.1
V_REF + 0.1
1.7
1.8
1.9
0.833
0.900
0.969 V_REF - 0.125 V_REF + 0.125
2.3
2.5
2.7
1.15
1.25
1.35 V_REF - 0.125 V_REF + 0.125
Notes:
1. Descriptions of the symbols used in this table are as follows:
V_CCO – the supply voltage for output drivers
V_REF – the reference voltage for setting the input switching threshold
V_IL – the input voltage that indicates a Low logic level
V_IH – the input voltage that indicates a High logic level
2. The V_CCO rails supply only output drivers, not input circuits.
3. For device operation, the maximum signal voltage (V_IH max) may be as high as V_IN max. See Table 72 in DS312.
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the V_CCAUX rail (2.5V).
The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V
configuration interface, apply 2.5V to the V_CCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.
6. For information on PCI IP solutions, see www.xilinx.com/pci.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
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