XA3S500E-4PQG208I Datasheet, PDF (32/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

R
Slave Parallel Mode Timing
Table 39: Timing for the Slave Parallel Configuration Mode
Symbol
Description
Clock-to-Output Times
T_SMCKBY
The time from the rising transition on the CCLK pin to a signal transition at the
BUSY pin
Setup Times
T_SMDCC
The time from the setup of data at the D0-D7 pins to the active edge the CCLK
pin
T_SMCSCC
T_SMCCW(2)
Hold Times
Setup time on the CSI_B pin before the active edge of the CCLK pin
Setup time on the RDWR_B pin before active edge of the CCLK pin
T_SMCCD
The time from the active edge of the CCLK pin to the point when data is last
held at the D0-D7 pins
T_SMCCCS
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the CSO_B pin
T_SMWCC
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the RDWR_B pin
Clock Timing
T_CCH
T_CCL
F_CCPAR
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
Not using the BUSY pin⁽²⁾
Using the BUSY pin
With bitstream compression
-4 Speed Grade
Min
Max
-
12.0
11.0
-
10.0
-
23.0
-
1.0
-
0
-
0
-
5
-
5
-
0
50
0
66
0
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6.
2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
3. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
32