XA3S500E-4PQG208I Datasheet, PDF (27/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Table 29: Switching Characteristics for the DFS
Symbol
Output Frequency Ranges
CLKOUT_FREQ_FX
Output Clock Jitter^(2,3)
CLKOUT_PER_JITT_FX
Duty Cycle^(5,6)
CLKOUT_DUTY_CYCLE_FX
Phase Alignment⁽⁶⁾
CLKOUT_PHASE_FX
CLKOUT_PHASE_FX180
Lock Time
LOCK_FX⁽²⁾
Description
Frequency for the CLKFX and CLKFX180 outputs
Period jitter at the CLKFX and CLKFX180
outputs
CLKIN <20 MHz
CLKIN > 20 MHz
Duty cycle precision for the CLKFX and CLKFX180 outputs,
including the BUFGMUX and clock tree duty-cycle distortion
Phase offset between the DFS CLKFX output and the DLL CLK0
output when both the DFS and DLL are used
Phase offset between the DFS CLKFX180 output and the DLL
CLK0 output when both the DFS and DLL are used
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts LOCKED
when the CLKFX and CLKFX180 signals
are valid. If using both the DLL and the DFS,
use the longer locking time.
5 MHz < F_CLKIN <
15 MHz
F_CLKIN > 15 MHz
Device
All
All
All
All
All
All
-4 Speed Grade
Min
Max
Units
5
311
MHz
Typ
Max
See Note 4
ps
±[1% of ±[1% of ps
CLKFX CLKFX
period period
+ 100] + 200]
-
±[1% of ps
CLKFX
period
+ 400]
-
±200
ps
-
±[1% of ps
CLKFX
period
+ 300]
-
5
ms
-
450
μs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 28.
2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
3. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching). Output
jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching
frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
4. Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter. Use the
Clocking Wizard to determine jitter for a specific design.
5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6. Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies a maximum jitter
of “±[1% of CLKFX period + 300]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 300 ps] = ±400 ps.
Phase Shifter
Table 30: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol
Description
Operating Frequency Ranges
PSCLK_FREQ
(F_PSCLK)
Frequency for the PSCLK input
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
-4 Speed Grade
Min
Max
Units
1
167
MHz
40%
60%
-
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
27