XA3S500E-4PQG208I Datasheet, PDF (19/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Table 19: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Single-Ended
V_REF (V)
Inputs
V_L (V)
V_H (V)
Outputs
R_T (Ω)
V_T (V)
LVTTL
-
0
3.3
1M
0
LVCMOS33
-
0
3.3
1M
0
LVCMOS25
-
0
2.5
1M
0
LVCMOS18
-
0
1.8
1M
0
LVCMOS15
-
0
1.5
1M
0
LVCMOS12
-
0
1.2
1M
0
PCI33_3
Rising
-
Note 3
Note 3
25
0
Falling
25
3.3
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
Differential
0.9
V_REF – 0.5
V_REF + 0.5
50
1.1
V_REF – 0.5
V_REF + 0.5
50
0.9
V_REF – 0.5
V_REF + 0.5
50
1.25
V_REF – 0.75
V_REF + 0.75
50
0.9
1.8
0.9
1.25
LVDS_25
BLVDS_25
MINI_LVDS_25
LVPECL_25
RSDS_25
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
-
V_ICM – 0.125 V_ICM + 0.125
50
-
V_ICM – 0.125 V_ICM + 0.125
1M
-
V_ICM – 0.125 V_ICM + 0.125
50
-
V_ICM – 0.3
V_ICM + 0.3
1M
-
V_ICM – 0.1
V_ICM + 0.1
50
-
V_REF – 0.5
V_REF + 0.5
50
-
V_REF – 0.5
V_REF + 0.5
50
-
V_REF – 0.5
V_REF + 0.5
50
-
V_REF – 0.5
V_REF + 0.5
50
1.2
0
1.2
0
1.2
0.9
1.8
0.9
1.25
Notes:
1. Descriptions of the relevant symbols are as follows:
V_REF – The reference voltage for setting the input switching threshold
V_ICM – The common mode input voltage
V_M – Voltage of measurement point on signal transition
V_L – Low-level test voltage at Input pin
V_H – High-level test voltage at Input pin
R_T – Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required
V_T – Termination voltage
2. The load capacitance (C_L) at the Output pin is 0 pF for all signal standards.
3. According to the PCI specification.
Inputs and
Outputs
V_M (V)
1.4
1.65
1.25
0.9
0.75
0.6
0.94
2.03
V_REF
V_REF
V_REF
V_REF
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
19