W90210F Datasheet, PDF (9/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
PDA[31:0]
STOP#
TRDY#
DEVSEL#
C/BE[3:0]#
FRAME#
IRDY#
PPAR
DMA Interface
tri-state
I/O
34-38, 40-41, 43,
45-52, 68-75, 78-
79, 81-86
I/O
60
I/O
58
I/O
59
I/O
44,53,66,76
I/O
55
I/O
56
I/O
65
PCI tri-state Address/Data bus, Address and Data are multiplexed
on the same PCI pins. A bus transaction consists of an address
phase followed by one or more data phases. PCI supports both
read and write bursts. The address phase is the clock cycle in
which FRAME# is asserted. During the address phase PDA[31:0]
contain a physical address. During data phases PDA[7:0] contain
the least significant byte (lsb) and PDA[31:24] contain the most
significant byte (msb). Write data is stable and valid when IRDY# is
asserted and read data is stable and valid when TRDY# is
asserted. Data is transferred during those clocks where both
IRDY# and TRDY# are asserted.
PCI Stop indicates the current target is requesting the master to
stop the current transaction.
PCI Target Ready indicates the selected device’s ability to
complete the current data phase of the transaction. A data phase
is completed on any clock both TRDY# and IRDY# are sampled
asserted. During a read, TRDY# indicates that valid data is present
on PDA[31:0]. During a write, it indicates the target is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY#
are asserted together.
PCI Device Select, when actively driven, indicates the driving
device has decoded its address as the target of the current
access. As an input, DEVSEL# indicates whether any device on
the bus has been selected.
PCI Bus Command and Byte Enables are multiplexed on the
same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase
C/BE[3:0]# are used as Byte Enables. The Byte Enables are valid
for the entire data phase and determine which byte lanes carry
meaningful data. C/BE[0]# applies to byte 0 (lsb) and C/BE[3]#
applies to byte 3 (msb).
PCI Cycle Frame is driven by the current master to indicate the
beginning and duration of an access. FRAME# is asserted to
indicate a bus transaction is beginning. While FRAME# is
asserted, data transfers continue. When FRAM# is deasserted,
the transaction is in the final data phase or has completed.
PCI Initiator Ready indicates the bus master’s ability to complete
the current data phase of the transaction. A data phase is
completed on any clock both IRDY# and TRDY# are sampled
asserted. During a write, IRDY# indicates that valid data is present
on PDA[31:0]. During a read, it indicates the master is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY#
are asserted together.
PCI Parity is even parity across PDA[31:0] and C/BE[3:0]#. PPAR
is stable and valid one clock after the address phase. For data
phases, PPAR is stable and valid one clock after either IRDY# is
asserted on a write transaction or TRDY# is asserted on a read
transaction. (PPAR has the same timing as PDA[31:0], but it is
delayed by one clock.) The mater drives PPAR for address and
write data phases; the target drives PPAR for read data phase.
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Version 1.4, 10/8/97