W90210F Datasheet, PDF (15/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
CR 11
CR 16
CR 26, 27
Others
read/write at any privilege level
PSW 'S'=0: read/write by any privilege level
PSW 'S'=1: read/write by privileged software
readable at any privilege level
writable at the most privileged level
Accessible only at most privileged level
Table 5.4 Access of control registers
5.2.5 W90210F External Interrupt Request register (EIRR; CR23)
Bit
EI[0:4]
External
Description
Number
Interrupt
0
00000
Timer_Int Interval Timer (CR16) interrupt request
1
10000
-
2
01000
-
3
11000
Serial
Serial port interrupt request from COM2
4
00100
INTA
PCI bus INTA# interrupt request
5
10100
INTB
PCI bus INTB# interrupt request
6
01100
INTC
PCI bus INTC# interrupt request
7
11100
INTD
PCI bus INTD# interrupt request
8
00010
Parallel_Int Parallel port interrupt request
9
10010
Serial_Int Serial port interrupt request from COM1
10
01010
DMA_Int DMA interrupt request
11
11010
TC_Int
Timer/Counter interrupt request
12 - 31
-
-
Reserved
Table 5.5 External Interrupt Request Register
5.2.6 AIRs (Architecture Invisible Registers)
There are eight AIRs in the W90210F. AIR[0] controls the internal cache configuration, burst mode, and default
endian. AIR[0] is documented in this data sheet. AIR[1] and AIR[2] are reserved for chip testing by Winbond, and their
functions will not be disclosed to users. Attempting to access these two registers may cause programs to be executed
with unpredictable results. Memory configuration registers are used for programming the configuration of W90210F
memory space. AIR[7] is the PCO register, this AIR can only be accessed through the JTAG ICE interface.
AIR[0]
Internal configuration register
AIR[1]
PSW register
AIR[2]
TMR register
AIR[3]
Memory configuration register 1
AIR[4]
Memory configuration register 2
AIR[5]
Memory configuration register 3
AIR[6]
Memory configuration register 4
AIR[7]
PCO register (program counter)
Table 5.6 W90210F CPU core AIRs
Important: Enabling or disabling the internal I-cache with MTAIR[0] will invalidate all I-cache entries automatically.
Enabling the internal D-cache with MTAIR[0] will invalidate all cache entries without dirty data entries being written back.
Disabling the D-cache, however, will not invalidate cache entries.
Disabling the internal D-cache with MTAIR[0] will cause dirty data to be left in the D-Cache and not
automatically written into memory. When a program references the dirty data location, stale data in memory will be
returned. To prevent this, a cache invalidation routine should be performed before the internal D-cache is disabled. The
invalidation routine must flush all cache entries one by one. This will invalidate the cache and also write back any dirty
data.
AIR[1] and AIR[2] are reserved registers and should never be written to or read from them. Accessing these
registers will cause unpredictable result.
5.3 Implementation of the PA-RISC instructions
15
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Version 1.4, 10/8/97