W90210F Datasheet, PDF (28/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
03h
[0:7]
04h
[0:7]
05h
[0:7]
06h
[0:7]
07h
[0:7]
08h
[0:7]
09h
[0:7]
0ah
[0:7]
0bh
[0:7]
ROM bank 1 base address register[8:15]
ROM bank 2 base address register[0:7]
ROM bank 2 base address register[8:15]
ROM bank 3 base address register[0:7]
ROM bank 3 base address register[8:15]
The register 0~7 has no default value.
[0:3] ROM bank 0 size.
[4:7] ROM bank 1 size.
[0:3] ROM bank 2 size.
[4:7] ROM bank 3 size.
0XXX → disable.
1000 → 64K, 1001 → 128K, 1010 → 256K, 1011→ 512K,
1100 → 1M, 1101 → 2M, 1110→ 4M, 1111→ 16M.
The default value is 0.
[0:1] bank 3 band width: 00→ 8_bit, 01→ 16_bit, 10→ 32_bit, 11→ reserved
[2:3] bank 2 band width: 00→ 8_bit, 01→ 16_bit, 10→ 32_bit, 11→ reserved
[4:5] bank 1 band width: 00→ 8_bit, 01→ 16_bit, 10→ 32_bit, 11→ reserved
[6:7] bank 0 band width: 00→ 8_bit, 01→ 16_bit, 10→ 32_bit, 11→ reserved
The default width of bank 0~3 is set by memory data bus bit 30 and 31.
[0:2] ROM access wait state.
000 → wait 2 state. 001→ wait 3 state.
010 → wait 4 state. 011→ wait 5 state.
100 → wait 6 state. 101→ wait 7 state.
110 → wait 8 state. 111→ wait 9 state.
The default wait state is8.
[3] access ROM bank0 only. Default bank0 only.
[4] LA mode. Default LA mode.
Index
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
DRAM Controller Register
Bit No. Description
[0:7]
DRAM bank 0 base address register[0:7]
[0:7]
DRAM bank 0 base address register[8:11]
[0:7]
DRAM bank 1 base address register[0:7]
[0:7]
DRAM bank 1 base address register[8:11]
[0:7]
DRAM bank 2 base address register[0:7]
[0:7]
DRAM bank 2 base address register[8:11]
[0:7]
DRAM bank 3 base address register[0:7]
[0:7]
DRAM bank 3 base address register[8:11]
The registers 20~27 has no default value.
[0:7]
[0:1] DRAM bank 3 type : 00→ 256K, 01 → 1M, 10 → 4M, 11 → 16M,
[2:3] DRAM bank 2 type : 00→ 256K, 01 → 1M, 10 → 4M, 11 → 16M,
[4:5] DRAM bank 1 type : 00→ 256K, 01 → 1M, 10 → 4M, 11 → 16M,
[6:7] DRAM bank 0 type : 00→ 256K, 01 → 1M, 10 → 4M, 11 → 16M,
Default 256K type.
[0:7]
[0] Parity check enable. (default 0)
[1] Enable DRAM bank 3.(default 0)
[2] Enable DRAM bank 2.(default 0)
[3] Enable DRAM bank 1.(default 0)
[4] Enable DRAM bank 0.(default 0)
[5] Disable DRAM address range from A0000 to FFFFF.(default 0)
[6] Fast write mode enable.(default 0)
[7] EDO fast page mode enable.(default 0)
28
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Version 1.4, 10/8/97