W90210F Datasheet, PDF (21/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
5.6 Interruptions
Interruptions are anomalies that occur during instruction processing causing the flow control to be passed to an
interruption handling routine. The interruptions are categorized into four groups based on their priorities. Interruption
numbers in table 5.17 are the individual vector numbers that determine which interruption handler is invoked for each
interruption. The group numbers determine when the particular interruption will be processed during the course of
instruction execution. The order the interruptions are listed within each group determines the priority of simultaneous
interruptions(from highest to lowest).
Group
1
2
3
4
interruption number
Interruption
1
High-priority machine check
2
Power failure interrupt
3
Recovery counter trap
4
External interrupt
5
Low-priority machine check
30
Instruction debug trap
8
Illegal instruction trap
9
BREAK instruction trap
10
Privileged operation trap
11
Privileged register trap
12
Overflow trap
13
Conditional trap
31
Data debug trap
22
Assist emulation trap
23
Higher-privilege transfer trap
24
Lower-privilege transfer trap
25
Taken branch trap
Table 5.17 Interruption number
Interruption handler routine begins execution at the address given by:
Interruption Vector Address + (32*interruption_number)
However, handler of HPMC will start at 'initial address + 4', where 'initial address is the first instruction address
issued by W90K after RESET. There are two initial address (determined by PA/486#) , X'000FFFF0 or X'EFFFFFF0.
HMPC handler will start from either X'000FFFF4 or X'EFFFFFF4. This arrangement is to ensure that HPMC handler will
start first at a ROM address that is more reliable than DRAM.
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Version 1.4, 10/8/97