W90210F Datasheet, PDF (16/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
The W90210F CPU core implements all the instructions specified in the PA-RISC Rev. 1.1 third edition.
W90210F executes these instructions with results that comply to the PA-RISC architecture. MMU related instructions
are executed by W90210F as defined in the PA-RISC architecture for a Level 0 processor. PA-RISC multimedia
extension 1.0 instruction set is also supported by W90210F. To speed up multimedia operations in some applications,
three additional instructions are defined through the diagnostic instructions. In addition to that, debug SFU is provided to
enhance the debug capability. The chip also implements DIAG instructions defined by Winbond for chip testing,
diagnostics, and programming the internal AIR (architecture invisible register). These DIAG instructions comply with the
PA-RISC DIAG instructions.
5.3.1 Implementation of Level 0 instructions
In the Level 0 processor implementation, the S-fields of all instructions are ignored and have no effect on the
device functions. The following instructions for TLB handling are executed as null instructions, as specified in the
architecture reference manual:
Instruction
Function
PDTLB
PITLB
Purge data TLB
Purge instruction TLB
PDTLBE
PITLBE
IDTLBA
IITLBA
IDTLBP
IITLBP
Purge data TLB entry
Purge instruction TLB entry
Insert data TLB address
Insert instruction TLB address
Insert data TLB protection
Insert instruction TLB protection
Table 5.7 Instructions executed as null instructions
Table 5.8 lists the differences in instruction execution results in a Level 0 processor.
Instruction
Description
Difference
LPA
Load physical address
Undefined instruction
LCI
Load coherence index
Undefined instruction
LDWAX
Load word absolute index
Same as LDWX if priv=0
LDWAS
Load word absolute short
Same as LDWS if priv=0
STWAS
Store word absolute short
Same was STWS if priv=0
GATE
Gateway
Always promote priv to 0
BV
Branch vectored
Demote priv to any non zero value
BE
Branch external
Demote priv to any non zero value, IASQ is nonexistent
BLE
Branch and link external
RFI
Return from interrupt
IASQ is nonexistent
RFIR
Return from interrupt and restore
LDSID
Load space identifier
0 is written into specified GR
MTSP
Move to space register
Executed as null instruction
MTCTL
Move to control register
Executed as null instruction if target is 8,9,12,13,17 or
20
MFSP
Move from space register
is written into specified GR
MFCTL
Move from control register
0 is written into specified GR if source is 8,9,12,13,17 or
20
PROBER
Probe read access
Always set target GR to 1
PROBERI
Probe read access immediate
Always set target GR to 1
PROBEW
Probe write access
Always set target GR to 1
PROBEWI
Probe write access immediate
Always set target GR to 1
Table 5.8 Summary of Level 0 instruction differences
5.3.2 Implementation of cache-related instructions
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Version 1.4, 10/8/97