W90210F Datasheet, PDF (26/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
8. Megacells Description
8.1 DRAM Controller & ROM Controller
8.1.1 DRAM controller
The DRAM controller supports four separate banks of dynamic memory. Either X9 or X36 SIMMs are
supported. CAS#-before-RAS# refresh cycles are performed periodically, as determined by the refresh timer. The
DRAM controller must arbitrate between access requests and refresh requests. EDO fast page mode and parity check
are also supported.
Refresh Timer
RAS#[4]
DRAM Type Register
CAS#[4]
CPU interface
Bus
Interface
to
CPU core
Bank Base Address
Registers
DRAM Configuration
Register
DRAM Timing
Register
Figure 8.1 DRAM controller block diagram
MA[12]
MD[32]
WE#
For each bank of DRAM, there will be registers to specify the bank base address and the bank DRAM type:
Bank Base Address Register.
Bank Type Register.
DRAM Type Register is used to program the DRAM type of each bank.
DRAM Type
00 : 256K DRAM cell
01 : 1M DRAM cell
10 : 4M DRAM cell
11 : 16M DRAM cell
01234567
Bank Bank Bank Bank
3210
DRAM Type Register
Figure 8.2 DRAM Type register programming
DRAM Timing Register is used to program DRAM timing parameters:
2ah
[6:7] Write cycle RAS# to CAS# delay.
[4:5] Read cycle RAS# to CAS# delay
[3] Write cycle CAS# pulse width.
[2] CAS# precharge time.
[0:1] RAS# precharge time.
2bh
[6:7] Read cycle. CAS# pulse width.
[5] Refresh cycle. CAS# active to RAS# active delay.
[3:4] Refresh cycle. RAS# active to CAS# inactive delay.
[1:2] Refresh cycle. RAS# active pulse width.
[0] Parity check enable.
26
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Version 1.4, 10/8/97