W90210F Datasheet, PDF (54/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
Move to AIR
Format:
0:5
5:10
05
t
6
5
Purpose:
Description:
Operation:
Exception:
Restriction:
Notes:
MTAIR r,t
MTAIR
11:15
21:25 26 27:31
r - - 00 - -
5 23 5 1 5
To copy value into a specified AIR from a general register.
If the AIR[t] is existed, the contents of GR[r] is copied into AIR[t]. If AIR[t] has n bits where
n<=32, the least significant n bits of GR[r] are moved into AIR[t].
if(t > 6)
undefined operation;
else if(priv != 0)
privilege instruction trap;
else
AIR[t] <-- GR[r];
Privilege instruction trap.
This instruction can be executed only by code running at the most privileged level.
AIR[0]: Internal configuration register
- bit31: Internal I-Cache enable (0/1- disable/enable)
- bit30: Internal D-Cache enable (0/1- disable/enable)
- bit29: Burst write enable (0/1- disable/enable)
- bit28: Default endian bit (0/1- big/little endian)
- bit27: Trap step mode enable (0/1- disable/enable)
- bit26: reserved
- bit25: reserved
- bit24: Enter Sleep state
- bit23: Multiplier wait state (0/1- 0/1 wait state)
- bit22: Freeze 1st 1K of I-Cache (0/1- disable/enable)
- bit21: Freeze 2nd 1K of I-Cache (0/1- disable/enable)
- bit20: Freeze 3rd 1K of I-Cache (0/1- disable/enable)
- bit19: Freeze 4th 1K of I-Cache (0/1- disable/enable)
(default: 13'b0)
AIR[1]: PSW register (default: 32'h0)
AIR[2]: TMR (timer register)
AIR[3]: Non-cacheable Offset regisetr
AIR[4]: Non-cacheable Mask register
AIR[5]: Write-Through Offset register
AIR[6]: Write-Through Mask register
AIR[7]: PCO register (program counter)
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Version 1.4, 10/8/97