W90210F Datasheet, PDF (25/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
needed for the program execution (i.e., a data dependency is encountered) or when a second miss cycle occurs before
the first miss cycle is serviced. The "hit under miss" scheme helps to minimize the D-cache miss penalty.
Separate byte write enables are provided for store instructions. This feature enables the W90210F to execute
store byte(s) instructions without read-modify-write operation.
7.2.1 Write-through Cache Support
Normally, the data cache is a write-back cache. Range for the write-through cache address space can be
defined in the AIR.
Write-through base register[0:15]: This register defines the base address of the write-through address range.
Write-through region size register: This register defines the size of the write-through address range:
000: disable
001: 64K
010: 128K (base address must be multiple of 128K)
011: 256K (base address must be multiple of 256K)
100: 512K (base address must be multiple of 512K)
101: 1M (base address must be multiple of 1M)
110: 2M (base address must be multiple of 2M)
111: 4M (base address must be multiple of 4M)
Important: User must flush the data cache before setting up these two registers.
7.3 Non-cacheable address space
User can define two non-cacheable regions with sizes ranging from 64K to 4M Byte. BIU can use these two
ranges to decide whether current bus cycle is cacheable or not.
Non-cacheable base address register: This register defines the base address of the non-cacheable address
range.
Non-cacheable region size register: This register defines the size of the non-cacheable address range:
000: disable
001: 64K
010: 128K (base address must be multiple of 128K)
011: 256K (base address must be multiple of 256K)
100: 512K (base address must be multiple of 512K)
101: 1M (base address must be multiple of 1M)
110: 2M (base address must be multiple of 2M)
111: 4M (base address must be multiple of 4M)
The memory address space above 1MB, 2MB, 4MB, 8MB, 16MB, 64MB, 128MB or 256MB can also be turned
into a third non-cacheable region. This is defined by the system non-cacheable region register: 0000: all
cacheable
0001: above 1MB
0010: above 2MB
0011: above 4MB
0100: above 8MB
0101: above 16MB
0110: above 32MB
0111: above 64MB
1000: above 128MB
1001: above 256MB
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Version 1.4, 10/8/97