W90210F Datasheet, PDF (8/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

4. W90210F Pin Description
PIN Name
DIR
PIN #
CPU Signal
RST
I
24
PCLK
I
22
OSC
I
25
PCI LOCAL BUS
INTA#
INTB#
INTC#
INTD#
PREQ0#
PREQ1#
GNT0#
GNT1#
PLOCK#
I
87
88
89
91
I
32
33
O
30
31
I
61
PCIRST#
PCICLK
SERR#
O
27
O
28
I
63
PERR#
I/O
62
W90210F
DESCRIPTION
CPU RESET input, high active
CPU CLOCK input
14.318Mhz Oscillator input for Timer, UART
for more detail description of the PCI signals please refer to the PCI LOCAL BUS
SPECIFICATION
PCI Interrupt input, level senstive, low active signal. Once the
INTx# signal is asserted, it remains asserted until the device driver
clear the pending request. When the request is cleared, the device
deasserts its INTx# signal.
PCI Request input, indicates to the PCI arbiter that this agent
desires use of the bus.
PCI Grant output, indicates to the agent that access to the bus
has been granted.
PCI Lock signal, indicates an atomic operation that may require
multiple transactions to complete. When PLOCK# is asserted,
non-exclusive transactions may proceed to an address that is not
currently locked.
PCI Reset output, is used to bring PCI-specific registers,
sequencers, and signals to a consistent state. Low active.
PCI Clock output, provides timing for all transactions on PCI and is
an input to every PCI device.
PCI System Error is for reporting address parity errors, data parity
errors on the Special Cycle command, or any other system error
where the result will be catastrophic. The assertion of SERR# is
synchronous to the clock and meets the setup and hold times of
all bused signals.
PCI Parity Error is only for the reporting of data parity errors during
all PCI transactions except a Special Cycle. The PERR# pin is
sustained tri-state and must be driven active by the agent receiving
data two clocks following the data when a data parity error is
detected. The minimum duration of PERR# is one clock for each
data phase that a data parity error is detected. An agent cannot
report a PERR# until it has claimed the access by asserting
DEVSEL# (for a target) and completed a data phase or is the
master of the current transaction.
8
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Version 1.4, 10/8/97