W90210F Datasheet, PDF (11/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

ROMRW#
O
ROMOE#
O
MA[0:11]
O
MD[0:31]
I/O
COM1 Serial Port Signal
SIN1
I
SOUT1
O
CTS1n
I
DSR1n
O
DTR1n
I
RTS1n
O
DCD1n
I
RIN1n
O
COM2 Serial Port Signal
SIN2
I
SOUT2
O
W90210F
15
16
206-208,1,3-4,6-
7,9-10,12-13
157-159,161-
162,164-167,169-
170,172-178,180-
181,183-194
FLASH ROM write enable. This signal is used to write data into
the mrmory in a ROM bank (such as Flash ROM).
ROM output enable. This signal enables the selected ROM Bank
to drive the MD bus.
Memory controller Memory Address bus. For DRAM access,
MA[0:11] is the DRAM row address and the DRAM column
address. For ROM/FLASH ROM access, MA[0:11] is the higher
portion ROM space address bits in the first ROM address cycle,
and the lower portion ROM space address bits after the first ROM
address cycle. MA[0] is the most significant bit (msb).
Memory controller Data bus for both DRAM data and ROM space
data. Bit 0 is the most significant bit (msb).
92
COM1 serial data input from the communication link (modem or
peripheral device).
94
COM1 serial data output to the communication link (modem or
peripheral device).
95
COM1 clear to send signal
96
COM1 data set ready
97
COM1 data terminal ready
98
COM1 request to send
100
COM1 data carrier detect
103
COM1 ring indicator
99
COM2 serial data input from the communication link (modem or
peripheral device).
101
COM2 serial data output to the communication link (modem or
peripheral device).
11
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Version 1.4, 10/8/97