W90210F Datasheet, PDF (33/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
8.4 Serial I/O
The serial I/O megacell implements a full-duplex, bi-directional UART with FIFO.
Peripheral
Interface
Input Buffer.
Input Shift Reg.
Output Buffer
Control Register
Status Register
Output Shift
Reg.
Control Logic
Timing generator
Serial I/O megacell
Figure 8.8 Serial I/O with FIFO
8.4.1 UART Register Definition
0 3F8, DLAB = 0 RBR[0:7]
0 3F8, DLAB = 0 THR[0:7]
1 3F9, DLAB = 0 IER[3:7]
Description
- Receiver Buffer Register.
- Read only.
- bit 7 is LSB.
- Transmitter Holding Register.
- Write only.
- bit 7 is LSB.
- Interrupt Enable Register.
SIN
SOUT
OSC
* bit 7: Irpt_RDA enable (1/0- Enable/Disable).
* bit 6: Irpt_THRE enable (1/0- Enable/Disable).
* bit 5: Irpt_RLS enable (1/0- Enable/Disable).
* bit 4: Irpt_MOS enable (1/0- Enable/Disable).
- bit 3: Loop-back enable (1/0- Enable/Disable).
0 3F8, DLAB = 1 DLL[0:7] * Divisor Latch Register (LS).
1 3F9, DLAB = 1 DLM[0:7] * Divisor Latch Register (MS).
2 3FA
IIR[0:7] - Interrupt Ident. Register.
- Read only.
* bit 7: No Irpt pending (1/0- True/False).
* bit 6: Irpt ID bit (2).
* bit 5: Irpt ID bit (1).
* bit 4: Irpt ID bit (0).
- bit 3: DMA mode select (1/0- Mode 1/Mode 0).
- bit 2: RCVR trigger (LSB).
- bit 1: RCVR trigger (MSB).
- bit 0: FIFO mode enable (1/0- Enable/Disable).
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Version 1.4, 10/8/97