W90210F Datasheet, PDF (32/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
8.3 Timer / Counter
Timer/Counter megacell
Peripheral
Interface
TCR1
TICR1
TCR2
TICR2
TCLK
TINT1
TINT2
Figure 8.7 Timer/Counter Megacell
Two 24-bit decrementing timers will be implemented. When the timer's interrupt enable bit is set to one and
the counter decrements to zero, the timer will assert the associated interrupt signal. The interrupt signal will assert one
of the 32 external interrupts defined by the EI bits in the control register. When a timer reaches zero, the timer
hardware reloads the counter with the value from the timer initial count register and continues decrementing.
Each timer is controlled and initialized by two registers: a timer control register and an timer initial count
register. These registers are all memory mapped I/O registers.
Timer Control register:
01234
23 24
31
TI CE IE
reserved
pre-scalar
TCR
Pre-Scalar (PS) : A pre-scalar value can be used to divide the input clock.
Interrupt Enable bit (IE): When IE is set to one and the counter decrements to zero, the timer asserts its
interrupt signal to interrupt the CPU.
Counter Enable bit (CE): Setting the CE bit to one causes the timer to begin decrementing. Setting the
CE bit to zero stops the timer.
Timer Interrupt bit (TI): The timer sets this bit to one to indicate that it has decrement to zero. This bit
remain one until software sets it to zero.
Timer Initial Count Register:
0
78
reserved
31
Timer Initial Count
TICR
A 24-bit read/write register for the initial counter value.
32
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Version 1.4, 10/8/97