W90210F Datasheet, PDF (24/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
7. On-Chip Cache Memories
The W90210F contains a 4-Kbyte instruction cache and a 2-Kbyte data cache. Cache memories hold
instructions and data that are repetitively accessed by the CPU and thus reduce the number of references that must be
made to the slower main memory. The internal cache uses a Harvard architecture, so the bandwidth between the cache
and processor is 2 words/cycle. Separate address and data bus are provided for I-cache and D-cache (Harvard
architecture).
After reset, both internal caches are disabled and all memory accesses are forwarded to the external bus.
AIR[0] is used to enable and disable the internal caches. A DIAG instruction (MTAIR) is the only instruction that can
access AIR[0].
The instruction cache is a direct mapped cache and the data cache is a 2-way set associative cache. Common
features for both caches are:
•4 words per entry
•One valid bit per entry
•Wrap-around fill
The line size is four words with a single valid bit for all four words. The line size is the same as that of an i486
processor, since the W90210F CPU core is designed to use an 486-type bus. Four words per entry is an optimal value,
considering the relatively small internal cache and the external bus bandwidth available.
The cache controller will request the BIU (Bus Interface Unit) for missed addresses. A whole line will be filled
after a cache miss, since only one valid bit is available. The BIU will first return the word needed (not necessarily the first
word in the entry) for program execution, and the processor will continue once the first word is returned. The remaining
three words will be filled into the cache while the program is executed; this is the so-called wrap-around refill scheme.
Important: Attempting to enable an internal cache after it has been enabled and then disabled will lead to
unpredictable results, because the internal cache may contain stale data. Hence a cache invalidation routine that flushes
all cache entries one by one must be performed before an internal cache is disabled. This will invalidate the cache and
cause any dirty data to be written back to memory.
7.1 Instruction cache
Instruction cache is a 4-Kbyte direct mapped cache. The instruction cache is divided into four 1-Kbyte caches,
and each 1-Kbyte cache can be freezed individually by setting the corresponding cache freeze bit in the AIR[0].
The cache freeze function must be implemented by the pre-load method. User must fill the instruction cache
with the desired routines by MTITAG and MTICAH diagnostic instructions and then set the corresponding freeze bit to
freeze the particular routine in the instruction cache.
7.2 Data cache
The integrated Data cache has several features that are not shared by the I-cache. The features listed below
have been added to enhance the efficiency of the D-cache:
• Write-back cache with write-through option
• Hit under miss
• Separate byte write enable
The integrated D-cache is a write-back cache by default. This minimizes the number of bus cycles needed
between the CPU and the slow main memory system. Data are written back to main memory only when an entry with
dirty data is to be replaced by a new address.
The address range for write-through cache option is programmable. User can program the write-through base
register and the write-through region size register (memory configuration registers) by MTAIR instruction.
The "hit under miss" scheme is used in the W90210F. A cache hit data reference is completed in one cycle.
When data miss occurs the W90210F will continue execution as long as the data are not needed. The BIU will perform
data access for the miss cycle in parallel with the program execution. While the BIU is accessing the missed data, the
internal D-cache can still be accessed by following load/store instructions. The W90K will stall only when missed data are
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Version 1.4, 10/8/97