W90210F Datasheet, PDF (3/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
6.1 Branch prediction
22
6.2 Load use interlock
23
7. ON-CHIP CACHE MEMORIES
24
7.1 Instruction cache
24
7.2 Data cache
24
7.2.1 Write-through Cache Support
25
7.3 Non-cacheable address space
25
8. MEGACELLS DESCRIPTION
26
8.1 DRAM Controller & ROM Controller
26
8.1.1 DRAM controller
26
8.1.2 ROM controller
27
8.1.3 Memory controller registers
27
8.2 DMA Controller (DMAC)
30
8.2.1 Register Description:
30
8.3 Timer / Counter
32
8.4 Serial I/O
33
8.4.1 UART Register Definition
33
8.5 Parallel Port
36
8.5.1 ECP Register Description
36
9. TIMING DIAGRAM
39
9.1 Memory controller
39
9.1.1 DRAM AC Timimg
39
9.1.2 ROM AC Timimg
39
9.2 DMA Controller
41
9.2.1 DMA device register read timing
41
9.2.2 DMA device register write timing
42
9.2.3 DMA demand mode data read cycles
43
9.2.4 DMA demand mode data write cycles
44
9.2.5 DMA block mode data read cycles
45
9.2.6 DMA block mode data write cycles
46
APPENDIX A. PA-RISC MULTIMEDIA INSTRUCTION SET
48
APPENDIX B. DIAGNOSTIC INSTRUCTIONS
53
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Version 1.4, 10/8/97