W90210F Datasheet, PDF (30/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
8.2 DMA Controller (DMAC)
The DMAC megacell provides two DMA channels to support DMA transfers between 8-bit I/O devices and main
memory. The DMA mechanism will provide two different methods for performing DMA transfers: demand-mode
transfers and block-mode transfers. The DMAC hardware is responsible for synchronizing transfers with memory or
external devices.
When the DMAC is configured for demand mode, an external device requests a DMA transfer with a request
input (DREQ1:0#). The DMAC acknowledges the requesting device with an acknowledge signal (DACK1:0#) when
the requesting device is accessed.
In block mode, DMA transfers are not requested by an external device. The DMA operation is initiated by software
and continued until terminated or suspended. The DMA operation is started when the enable bit in the Configuration
Register is set.
DMAC megacell
Bus
Interface
SSAR
TSAR
LETH
MODE
TXCOUNT
DREQ#[2]
DACK#[2]
IOR
IOW
IODATA[8]
DEV address
DA[12]
CS[2]
Figure 8.5 DMA controller
In programming the megacell registers, the register address is defined by the BASE register plus the offset value.
8.2.1 Register Description:
Source Starting Address Register (SSAR0=080, SSAR1=084): SSAR is a read/write 32-bit register that contains
the starting address of the DMA transfer source.
Target Starting Address Register (TSAR0=081, TSAR1=085): TSAR is a read/write 32-bit register that contains the
starting address of the DMA transfer target.
Length/Count Register (LETH0=082, LETH1=086): LETH is a read/write 32-bit register that records the counts of
current DMA transfer.
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Version 1.4, 10/8/97