W90210F Datasheet, PDF (5/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
1. General Description
The W90210F Embedded Controller is part of Winbond′s W90K Embedded processor family. The processor
is a high-performance, highly integrated 32-bit processor intended for a wide range of embedded applications, such as
set-top box, web browser, X-terminal, and visual/data communication devices..
The W90210F CPU core is based on the HP PA-RISC architecture and is upward code compatible with the
W90K. The PA-RISC architecture incorporates traditional RISC elements, such as instruction pipelining, a register-to-
register instruction set and a large, general-purpose register file. Separate on-chip instruction and data caches allow the
W90210F to fetch an instruction and access data in a single processor cycle.
The W90210F includes several features that greatly increase performance, reduce system component count
and ease the overall system design task. In addition to its cache memories, the W90210F′s on-chip support features
include a DRAM controller, ROM/FLASH ROM interface, PCI bridge, DMA controller, two serial ports with FIFO, IEEE
1284 parallel port, timer/counters, and enhanced debug support- all features that are commonly required in embedded
applications.
Figure 1.1 shows the system diagram of W90210F.
internal bus
PCI Bridge
W 9 0 K C P U c o re
Bus Interface Unit
DRA M
Interface
ROM /
FLASH ROM
Interface
DRAM array
Memory
Data
Bus
8/16/32-bit
ROM
latch
CPU RST, CPU CLOCK
Address/Control Bus
32-bit Data Bus
2-Channel
DMA
Controller
8-bit DMA
I/O Bus
Peripheral
Bridge
Serial
Ports
ECP
Timer
Figure 1.1 W90210F System Diagram
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The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Version 1.4, 10/8/97