W90210F Datasheet, PDF (13/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
0
GR 0
GR 1
GR 2
GR 30
GR 31
31
Permanent zero
Target for ADDIL or General use
General use
•
•
•
General use
Link register for BLE or General use
Figure 5.1 General Registers
5.2.2 Shadow registers
W90210F CPU core provides seven registers called shadow registers as defined in the PA-RISC architecture.
The contents of GR1,8,9,16,17,24 and 25 are copied upon interruptions. Shadow registers reduce the state save and
restore time by eliminating the need for general register saves and restores in interruption handlers. The behavior of the
shadow registers is described below.
Before entering interrupt routine: Contents of seven general registers are copied into shadow registers in one cycle.
When executing RFIR: Contents of shadow registers are copied into general registers automatically in one cycle.
5.2.3 Processor Status Word (PSW)
The processor state of W90K is encoded in a 32-bit register called the Processor Status Word (PSW). The
format of PSW is shown in figure 5.2. The old value of the PSW is saved in the Interrupt Processor Status Word (IPSW)
when interruption occurs. The PSW is set to the contents of the IPSW by the RFIR (RETURN FROM INTERRUPTION
and RESTORE) instruction.
111111 1
2 22222233
0 1 2 ... 4 5 6 7 8 9 0 1 2 3 4 5 6 ... 3 4 5 6 7 8 9 0 1
YZ
Field
rv E S T H L N X B C V M
C/B
Description
rv G F R Q P D I
rv
Reserved bits.
Y
Data debug trap disable.
Z
Instruction debug trap disable.
E
Little endian mode enable. When 1, all instruction fetches and loads/stores are little endian. The E bit after
RESET is set according to the state of ENDIAN pin.
S
Secure Interval Timer. When 1, the Interval Timer is readable only by code executing at the most privileged
level. When 0, the Interval Timer is readable by code executing at any privilege level.
T
Taken branch enable. When 1, any taken branch is terminated with a taken branch trap.
H
Higher-privilege transfer trap enable.
L
Lower-privilege transfer trap enable.
N
Nullify. The current instruction is nullified when this bit is 1.
X
Non-existent register bit.
B
Taken branch. The B-bit is set to 1 by any taken branch instruction and set to 0 otherwise.
C
Non-existent register bit.
V
Divide step correction. The integer primitive instruction records intermediate status in this bit to provide a
non-restoring divide primitive.
M
High-priority machine check mask. When 1, High Priority Machine Checks (HPMCs) are masked. Normally
0, this bit is set to 1 after HPMC and set to 0 after all other interruptions.
C/B
Carry/borrow bits. These bits are updated by some instructions from the corresponding carry/borrow
outputs of the 4-bit digit of the ALU.
G
Debug trap enable.
F
Non-existent register bit.
13
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Version 1.4, 10/8/97