W90210F Datasheet, PDF (12/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
5. W90210F CPU Core
The key characteristics of the W90210F CPU core have been designed specifically to meet the requirements of
embedded control applications. The following subsections describe the essential features of the W90210F CPU core,
including its architecture, implementations, and registers.
5.1 Architecture
The W90210F CPU core is designed based on the powerful PA-RISC architecture. Since our target is high-
end embedded applications, a great deal of design effort has been devoted to taking full advantage of this powerful
architecture.
5.1.1 PA-RISC Rev. 1.1 third edition
The core of the W90210F is a processor unit that complies with PA-RISC architecture Rev. 1.1 third edition
specifications. There are three kinds of operations to be executed by the processor; branch, load/store, and data transform.
Most RISC architecture chooses to execute one of the three operations in an instruction. On the contrary, most PA-
RISC instructions perform two operations listed above. For example, "ADD and BRANCH on the result of the ADD" can
be done with one PA-RISC instruction. W90210F CPU core implements these powerful instructions and executes them
in a single cycle. With such a powerful combined operation instruction set, the code size of W90210F can be much
smaller than other RISC system. With the single cycle execution capability of these instructions, W90210F deliver very
high throughput.
5.1.2 Level 0 implementation
In the PA-RISC architecture, a processor without an MMU is defined as the Level 0 implementation. All memory
and I/O accesses in a level 0 PA-RISC processor are in real mode. W90210F is a level 0 implementation of PA-RISC
architecture.
5.1.3 Multimedia Extension Instruction Set
The PA-RISC Multimedia extensions consists of a set of instructions which speed up the execution of common
operations found in multimedia applications. In a 32-bit integer datapath, each multimedia instruction allows generic
arithmetic operations to be executed in parallel on two pairs of 16-bit data. The PA-RISC multimedia extensions 1.0
instruction set is implemented by the W90210F CPU core.
5.2 CPU resources
The W90210F CPU core implements all the registers needed for a Level 0 processor as defined in the PA-
RISC specifications. Some registers or register bits are not needed in a Level 0 processor and are defined as
nonexistent registers or register bits. The W90210F CPU implements three AIRs (Architecture Invisible Registers) that
can be accessed by executing DIAG instructions.
5.2.1 General registers
Thirty-two 32-bit general registers provide the central resource for all computation. They are numbered GR 0
through GR 31, and are available to all program at all privilege levels. GR 0, when referenced as source operand,
delivers zeros. When GR 0 is used as destination, the result is discarded. GR 1 is the target of the ADD IMMEDIATE
LEFT instruction. GR 31 is the instruction address offset link register for the base relative interspace procedure call
instruction. GR 1 and GR 31 can also be used as general register.
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Version 1.4, 10/8/97