W90210F Datasheet, PDF (27/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
DRAM configuration register is used to program the DRAM configuration:
[7] EDO fast pagemode enable.
[6] Fast write mode enable
[5] Disable DRAM address range from A0000 to FFFFF
[4] Enable DRAM bank 0.
[3] Enable DRAM bank 1.
[2] Enable DRAM bank 2.
[1] Enable DRAM bank 3.
The refresh timer is a decrementing timers, which are clocked by a separated clock from the system clock.
When the refresh timer reaches zero, the refresh timer will generate a DRAM refresh request.
8.1.2 ROM controller
The ROM controller also supports upto four banks of ROM and the ROM can be 8-bit, 16-bit, or 32-bit.
Bank Base/Size
Registers
CPU Interface
Bus
Interface
ROM and FLASH
Configure Register
ROM/FLASH Read
Wait State
Register
MA
latch enable
cs#[4]
oe#
r/w#
ROM Address
8-bit/
16-bit/
32-bit
ROM/
FLASH
Memory Data
Figure 8.3 ROM controller diagram
For each bank of ROM, two registers are used to specify the bank address range:
ROM Bank Base Address Register.
ROM Bank Size Register.
ROM Configuration Register is used to program the ROM data bus size of each bank.
ROM Bus Size
00 : 8-bit ROM
01 : 16-bit ROM
10 : 32-bit ROM
11 : reserved
01234567
Bank Bank Bank Bank
3210
ROM Configuration Register
Figure 8.4 ROM configuration register programming
ROM Wait State Register is used to program the number of wait states needed to access ROM.
8.1.3 Memory controller registers
In Memory Controller, two IO ports are used to access the entire register set: the index port is at address 22h
and the data port is at address 23h. To access a register, first write the index into the index port and then read or write
the data through the data port. The internal register for the memory controller is listed as follows:
ROM controller register :
Index
Bit No. Description
00h
[0:7]
ROM bank 0 base address register[0:7]
01h
[0:7]
ROM bank 0 base address register[8:15]
02h
[0:7]
ROM bank 1 base address register[0:7]
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Version 1.4, 10/8/97