W90210F Datasheet, PDF (22/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

W90210F
6. Pipeline Architecture
The pipeline used in the W90210F CPU core is a typical five-stage pipeline. Most instructions are executed in
one single cycle except long instructions. Long instructions are FDC, FDCE, FIC, FICE, PDC, RFIR, and RFI. For
Branch instruction, one delay slot is needed.
The pipeline is shown below:
CLK
CLK
CLK
CLK
CLK
CLK
CLK
IA
IF
FR
EX
MM
WB
IA
IF
FR
EX
MM
WB
IA
IF
FR
EX
MM
WB
IA: Instruction address calculation
IF: Instruction fetch
FR: Register fetch and decode
EX: Execution and data address calculation
MM: Memory reference for Load/Store instruction
WB: Write back to register file
Figure 6.1 W90K pipeline architecture
IA: The instruction address for the cycle is generated. The sources of the instruction address are n+1, branch
target, interrupt vector, IIAOQ, and reset pointer. The address is calculated and selected within half cycle.
IF: Instruction cache is fetched during this cycle. Instruction will be available before end of IF. IMISS (instruction
cache miss) will be available at the second half of IF.
FR: The instruction from IF stage is used to access the register file and decoded for execution. The bypass
control is also generated to select the correct bypass path. If the instruction is a cache miss, the pipeline will stall at this
stage.
EX: The instruction is executed in this stage. For branch instructions, a dedicated adder is used to calculate the
target address at the first half of EX (corresponding to the IA stage of the instruction after the delay slot). The condition
check is also performed in this stage for conditional branch instruction. Data address for memory reference instruction is
also calculated in this stage. For non-nullified MTCTL instruction, data will be written into CR at the end of the EX stage.
External traps (EI, HPMC, LPMC and PFW) will be sampled at the EX stage and piped to the WB stage for trap
handling.
MM: The data cache is referenced at this stage.
WB: The data from EX or MM stage will be written back to register file in the first half of the WB stage. The data
can be read out by the FR stage in the same cycle; otherwise one extra bypass will be needed. If the MM stage of this
instruction is a miss and a data dependence exists, the pipeline will stall at the WB stage; otherwise, the pipeline will
continue.
6.1 Branch prediction
Static branch prediction is used for conditional branch instructions in W90210F CPU core.
Forward branch: predict not taken
Backward branch:predict taken
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Version 1.4, 10/8/97