W90210F Datasheet, PDF (34/67 Pages) Winbond – PA-RISC EMBEDDED CONTROLLER

2 3FA
3 3FB
4 3FC
5 3FD
6 3FE
7 3FF
W90210F
FCR[0:7] - FIFO Control Register.
- Write only.
LCR[0:7]
* bit 7: FIFO mode enable (1/0- Enable/Disable).
- bit 6: Reset RCVR FIFO. (self_clearing bit)
- bit 5: Reset XMIT FIFO. (self_clearing bit)
- bit 4: DMA mode select (1/0- Mode 1/Mode 0).
- bit 3: (Reserve).
- bit 2: (Reserve).
* bit 1: RCVR trigger (LSB).
* bit 0: RCVR trigger (MSB).
- Line Control Register.
TOR[0:7]
* bit 7: Word length select (LSB).
* bit 6: Word length select (MSB).
- bit 5: Number of stop bit.
- bit 4: Parity enable. (1/0- Enable/Disable)
- bit 3: Even parity select. (1/0- Even/Odd parity)
- bit 2: Stick parity enable. (1/0- Enable/Disable)
- bit 1: Set break.
- bit 0: Divisor Latch Access Bit (DLAB).
- Time Out Register.
LSR[0:7]
- bit 7 ~ 1: Time out bit-count.
- bit 0: Irpt_TOUT enable. (1/0- Enable/Disable)
- Line Status Register.
- Read only.
- Write: Null operation.
MOS[0:7]
SCR[0:7]
- bit 7: Data Ready (DR).
- bit 6: Overrun Error (OE).
- bit 5: Parity Error (PE).
- bit 4: Framing Error (FE).
- bit 3: Break Interrupt (BI).
- bit 2: THR Empty (THRE).
- bit 1: Transmitter Empty (TEMT).
- bit 0: Error in RCVR FIFO (Err_RCVR).
- MODEM Status Register: non-exist
- Write: Null operation.
- Read: Get 8'b0
- Scratchpad Register.
- Read/Write-able
Note: 1. Irpt_RDA: Received Data Available interrupt.
Irpt_THRE: Transmitter Holding Register Empty interrupt.
Irpt_RLS: Receiver Line Status Interrupt.
Irpt_MOS: MODEM Status Interrupt.
Irpt_TOUT: Receiver Time OUT Interrupt.
2. Baud rate = Frequency input / (16 * ({DLM, DLL} + 2))
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Version 1.4, 10/8/97