NS32FV100 Datasheet, PDF (78/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

4 0 Device Specifications (Continued)
4 6 2 Timing Tables (Continued)
4 6 2 2 Input Signal Requirements (Continued)
Symbol Figure Description
Reference
Condition
NS32FX200-15
Min
Max
NS32FX200-20
Min
Max
NS32FX200-25
Min
Max
Units
t_ADSs
4-9 ADS Signal
Before R E
51
36
27
ns
Setup
CTTL T2
t_ADSw
4-9 ADS Pulse
At 0 8V
20
15
10
ns
Width
(Both Edges)
t_Ds
4-16 Data Setup
Before R E
15
14
10
ns
CTTL T4
t_Dh
t_HBEs
t_HBEh
t_DDINs
t_DDINh
t_HLDAs
t_HLDAh
t_SDINs
t_SDINh
t_SVIs
t_SVIh
t_SBGs
t_SBGh
t_PFAILs
t_PFAILh
t_INTs
4-16
4-9
4-9
4-9
4-9
4-16
4-16
4-19
4-19
4-27
4-27
4-27
4-27
4-22
4-22
4-18
Data Hold
After R E
CTTL T4
0
0
0
ns
HBE Signal
Before R E
51
36
27
ns
Setup
CTTL T2
HBE Signal
After R E
0
0
0
ns
Hold
CTTL next T1 i
DDIN Signal
Before R E
Setup
CTTL T2
51
36
27
ns
te ^{DDIN Signal}
After R E
0
0
0
ns
Hold
CTTL next T1 i
HLDA Signal
Before R E
51
36
27
ns
Setup
CTTL Ti
HLDA Signal
After R E
0
0
0
ns
le ^Hold
CTTL Ti
SDIN Signal
Before F E
ns
Setup
CTTL
15
14
12
SDIN Signal
After F E
0
0
0
ns
Hold
CTTL
SVI Signal Setup After L E
o _{(Notes 1 2)}
SNH
t_SCMPRW
b 200 ns
t_SCMPRW
b 200 ns
t_{SCMPRW ns}
b 200 ns
SVI Signal
After L E
Hold
Next SNH
0
0
0
ns
s SBG Signal Setup After L E
(Notes 1 2)
SNH
t_SCMPRW
b 200 ns
t_SCMPRW
b 200 ns
t_{SCMPRW ns}
b 200 ns
SBG Signal
After L E
0
0
0
ns
Hold
Next SNH
b PFAIL Signal
Before R E
15
14
13
ns
Setup
CTTL
PFAIL Signal
After R E
Hold
CTTL
0
0
0
ns
O^{INT0–3 Signal Before R E}
15
14
13
ns
Setup
CTTL
t_INTh
4-18 INT0–3 Signal After R E
0
0
0
ns
Hold
CTTL
Note 1 t_SCMPRW e (SCMPRW a 1) t_CTp while SCMPRW is the programmed value in SCMPRW register The current tolerance is 8 mA
Note 2 The internal analog reset width as programmed in the SCMPRW register should be more than 200 ns The analog reset should be terminated at least 300
ns before the next SNH leading edge
77