NS32FV100 Datasheet, PDF (57/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

3 0 System Interface (Continued)
FIGURE 3-7 Zone 2 (DRAM) Refresh Transaction Zero Wait State
TL EE 11331 – 39
lete_{TL EE 11331–40}
If a new CPU DMA transaction to either Zone 0 1 or 2 is started during the refresh transaction it is postponed by CWAIT until the refresh is completed and for at
least two more cycles (postponed T1 T2)
o FIGURE 3-8 Zone 2 (DRAM) Refresh Transaction Three Wait States
Obs ^{Figure 3-9 shows the Freeze Mode refresh transaction waveforms with RCFG RFRT e 5}
FIGURE 3-9 Freeze Mode Refresh Transaction Waveform
TL EE 11331 – 41
56