NS32FV100 Datasheet, PDF (75/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

4 0 Device Specifications (Continued)
4 6 2 Timing Tables (Continued)
4 6 2 1 Output Signals Internal Propagation Delays (Continued)
Symbol
t_SMPHa
t_SMPHia
t_STBa
t_STBia
t_PMPHa
t_PMPHia
t_BUZCLKa
t_BUZCLKia
t_WDTa
t_INTRa
t_INTRia
t_MWSKa
t_MWSKia
t_DMAKa
t_DMAKia
t_PEXTa
t_PEXTia
t_PDOEv
t_PDOIv
t_PCLKa
t_PCLKia
Figure
4-23
4-23
4-21
4-21
4-21
4-21
4-26
4-26
4-22
4-18
4-18
4-25
4-25
4-16
4-16
4-26
4-26
4-21
4-21
4-21
4-21
Description
Reference
Condition
NS32FX200-15 NS32FX200-20 NS32FX200-25
Units
Min Max Min Max Min Max
SMPH0–3 Signal
Active
After R E
CTTL
24
22
20
ns
SMPH0–3 Signal
Inactive
After R E
CTTL
24
22
20
ns
STB0–3 Signal
Active
After R E
CTTL
t_CTp2 t_CTp2 t_CTp2 t_CTp2 t_CTp2 t_CTp2
ns
a 24
a 22
a 20
STB0–3 Signal
Inactive
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
PMPH0-3 Signal
Active
After R E
CTTL
24
22
20
ns
PMPH0–3 Signal
Inactive
After R E
CTTL
24
22
20
ns
BUZCLK Signal
Active
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
te ^{BUZCLK Signal}
Inactive
After R E
CTTL
t_{CTp 2}
t_{CTp 2}
a24
t_{CTp 2}
t_{CTp 2}
a22
t_{CTp 2}
t_{CTp 2}
a20
ns
WDT Signal
Active
After R E
CTTL
24
22
20
ns
INTR Signal
le ^Active
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
INTR Signal
Inactive
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
MWSK Signal
Active
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
MWSK Signal
o _Active
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
DMAK0–3 Signal
Active
After R E
CTTL
24
22
20
ns
s DMAK0–3 Signal
Inactive
After R E
CTTL
24
22
20
ns
PEXT Signal
Active
After R E
CTTL
24
22
22
ns
b PEXT Signal
Inactive
After R E
CTTL
24
22
22
ns
PDO Signal Valid
After F E PCLK
(External Clock Mode) Input
33
33
33
ns
O^{PDO Signal Valid}
After R E CTTL
26
24
22
ns
(Internal Clock Mode) (Note 1)
PCLK Signal
Active
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
PCLK Signal
Inactive
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
Note 1 PDO is changed on the first CTTL R E following the PCLK F E
74