NS32FV100 Datasheet, PDF (33/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

2 0 Architecture (Continued)
(3) The OVR bit in the STAT register is set to ‘‘1’’
and the EOVR bit is ‘‘1’’ In the last case the
CHEN bit is forced to ‘‘0’’ and cannot be set to
‘‘1’’ by software unless the OVR is either
cleared or masked by clearing the EOVR bit in
the STAT register
VLD Transfer Parameter Valid Indicates whether the
transfer parameters for the next block to be trans-
ferred are valid The VLD bit is ignored in auto-ini-
tialize operation mode and is cleared by hardware
after ADRA and BLTR have been copied to ADCA
and BLTC respectively VLD is used to distinguish
between single transfer and double-buffer opera-
tion modes
2 6 6 Usage Recommendations
1 Before activating the DMA program the appropriate
Ports module registers PBDO PBMS PCDO PCMS and
PCEN to connect the DMA to the NS32FX100 I O pins
2 Set the MCFG register to allocate the DMA channels as
either internal or external as appropriate
3 The Ports module must be configured to allow the alloca-
tion of the I O pins to the DMA channels
2 6 7 DMAC Bus Cycles
lete _{FIGURE 2-15 DMA Fly-By Read Transaction (DIR e 0 NFBY e 0)}
TL EE 11331 – 20
The maximum throughput of a DMA channel is 12 5 Mbyte sec (Two bytes can be transferred at a rate of four CTTL cycles per
o _{transfer up to 25 MHz )}
Note 1 Memory control signals (like CWAIT select and write enable) are generated according to the specifications of the accessed zone
Obs ^{v Note 2 A in the figure indicates DMA priority resolving points}
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