NS32FV100 Datasheet, PDF (22/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

2 0 Architecture (Continued)
SLS Pulse Generation
Scan Line Sync (SLS) is generated by a timer according to a
calculated delay (in CTTL cycles) from the beginning of the
SPP pulse The delay between the beginning of SPP and
the leading edge of SLS SLS pulse width and SLS polarity
are software programmable
The first pixel clock after SPP may be distorted SLS must
be programmed so that this pixel is ignored
Active Video Window and Peak Detector Window
Generation
The active Video Window signaling the valid data window
and the Peak Detector Window signaling the programmable
window for Automatic Background Control are generated
by timers which are triggered by SPP and clocked by
SPCLK
Scanner Interrupt Generation
The scanner interrupt is a rising-edge interrupt generated at
the beginning of a time slot which is defined by the Scanner
Interrupt Time-Slot register (SITSL)
2 4 2 3 Video Handling Block
The Video Handling Block is an Analog-to-Digital convertor
for the analog video signal It enables shading half-toning
and bi-level support with Automatic Background Control
(ABC) It also allows pixel generation control using external
circuitry
lete _{Note 1 The delay is controlled by the respective register (SLSD SAVWD or SPDWD)}
Note 2 Measured in CTTL cycles
Obso ^{Note3 MeasuredinSPCLKcycles}
FIGURE 2-8 Scanner Period Control Signals
TL EE 11331 – 13
FIGURE 2-9 Block Diagram of Scanner’s Video Handling Block
21
TL EE 11331 – 14