NS32FV100 Datasheet, PDF (32/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

2 0 Architecture (Continued)
DEC
NFBY
DIR
ADA
ADCA
ADRA
ADRB
BLTC
BLTR
Decrement Increment update of ADCA
STAT Status register This register has two functions
0 ADCA incremented after each transfer cycle (if
ADA e 1)
1 ADCA decremented after each transfer cycle (if
ADA e 1)
Fly-By Memory-to-I O Transfers for channel 3
only (for channels 0 1 2 reserved)
Holds status information for the DMA channel
Used to enable or mask the DMA interrupts for the
various terminations conditions
7
6
5
4
3
2
1
0
Res EOVR res
ETC CHAC OVR
res
TC
0 Fly-By
1 Memory-to-I O
Transfer Direction
Specifies the direction of the transfer between
memory and implied I O device
TC
OVR
Terminal Count
When set to ‘‘1’’ indicates that the transfer was
completed by a terminal count condition (BLTC)
reached 0)
Channel Overrun (Channels 1 3 only)
0 Implied I O Device is Destination
Set to ‘‘1’’ in non auto-initialize mode when the
1 Implied I O Device is Source
Device Address Control Controls the update of the
ADCA counter after each transfer cycle
0 ADCA address unchanged
1 ADCA address updated
Device Address Counter 32-bit register
te ^{Bits0–23}
Hold the current address of either the
source data item or the destination lo-
cation in the Addressed Device
Bits 24–31 Reserved
If the ADA bit in the MODE register is
set to ‘‘1’’ ADCA is updated accord-
ing to DEC and FBY bits in MODE reg-
ister after every DMA transfer
Device Address Register 32-bit register (Channels
le ^{1 and 3 only)}
Bits 0–23
Hold the starting address of the next
block to be transferred of either the
source data block or the destination
data area of the Addressed Device
Bits 24–31 Reserved
o ^{Implied I O Device register 32-bit register (Chan-}
nel 3 only)
Bits 0–23
Hold the address of either the source
data block or the destination data
area of the implied I O device
s _{Bits 24–31 Reserved}
Block Length Counter 32-bit register
Bits 0–23 Hold the current number of bytes to
be transferred
b _{Bits 24–31 Reserved}
BLTC is decremented after each transfer accord-
ing to FBY bit in MODE register
Block Length Register 32-bit register (Channels 1
and 3 only)
O^{Bits 0–23 Hold the number of bytes in the next}
CHAC
ETC
EOVR
present transfer is completed (BLTC e 0) but the
parameters for the next transfer are not valid (VLD
bit in CNTL is ‘‘0’’)
Channel Active Read Only
When set to ‘‘1’’ indicates that the channel is ac-
tive (CHEN bit in CNTL register is ‘‘1’’ and BLTC ^l
0)
This bit continuously reflects the active or inactive
status of the channel and therefore can only be
read Data written to the CHAC bit is ignored
Enables interrupt pulse when the BLTC counter
reaches 0
0 Disable
1 Enable
Enables interrupt pulse when OVR bit is set (Chan-
nels 1 3 only)
0 Disable
1 Enable
The TC and OVR bits are sticky This means that once set
by the occurrence of the specific condition they will remain
set until explicitly cleared by software Those bits can be
individually cleared by writing a value into the STAT register
with the bit positions to be cleared set to ‘‘1’’ Writing ‘‘0’’ to
those bits has no effect
CNTL
7
Control register
This register is used to synchronize the channel
operation with the programming of the block trans-
fer parameters
21
0
res
VLD CHEN
CHEN
Channel Enable
0 Channel Disable
1 Channel Enable
block to be transferred
The CHEN bit is cleared to ‘‘0’’ in the following
Bits 24–31 Reserved
cases
A ‘‘0’’ value in the BLTR register while the VLD
(1) Upon Reset
and CHEN in the CNTL register are both set to ‘‘1’’
(2) Software clears it by writing to the CNTL regis-
may cause unpredictable results
ter
31