NS32FV100 Datasheet, PDF (4/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

Table of Contents (Continued)
2 0 ARCHITECTURE (Continued)
3 0 SYSTEM INTERFACE (Continued)
2 11 Bus and Memory Controller (BMC)
45
3 3 Control of Power Consumption
53
2 11 1 Features
45
3 4 Bus Cycles
54
2 11 2 Operation
45
4 0 DEVICE SPECIFICATIONS
62
2 11 2 1 Zones 0 1 (ROM and SRAM)
Transactions
46
4 1 NS32FX100 Pin Descriptions
62
2 11 2 2 Zone 2 (Dynamic Memory)
4 1 1 Supplies
62
Transactions (NS32FX200 and
4 1 2 Input Signals
62
NS32FV100 only)
46
4 1 3 Output Signals
63
2 11 2 3 Zone 3 (I O) Transactions
47
4 1 4 Input Output Signals
64
2 11 2 4 Operation in Freeze Mode
47
4 2 Output Signal Levels
64
2 11 2 5 On-Chip Registers Access
47
4 2 1 Freeze Mode Output Signals
65
2 11 3 Registers
47
2 11 4 Usage Recommendations
48
2 12 Register Summary
48
2 12 1 NS32FX100 Registers Access Method 48
2 12 2 NS32FX200 NS32FV100 and NS32FX100
Registers
48
3 0 SYSTEM INTERFACE
53
te ^{3 1 Power and Grounding}
53
Obsole ^{32 ClocksandTrapsConnectivity}
53
4 2 2 Reset Power Restore Output Signals
65
4 3 Absolute Maximum Ratings
67
4 4 Electrical Characteristics
67
4 5 Analog Electrical Characteristics
69
4 6 Switching Characteristics
70
4 6 1 Definitions
70
4 6 2 Timing Tables
71
4 6 2 1 Output Signals Internal Propagation
Delays
71
4 6 2 2 Input Signal Requirements
76
APPENDIX A CODEC TRANSMISSION
PERFORMANCE
92
3