NS32FV100 Datasheet, PDF (42/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

2 0 Architecture (Continued)
2 9 3 Registers
Program the IELTG and ITRPL registers to con-
IVCT
Interrupt Vector register Read only 8-bit regis-
trol the ICU mode and polarity as follows
ter
7
6
5
0
0
1
4
3
0
0
INTVECT
IELTG
0
0
ITRPL
0
1
Mode
Low Level
High Level
INTVECT When INTR pin is active this field contains the
encoded value of the enabled pending interrupt
1
0
Falling Edge
1
1
Rising Edge
IENAM
IPEND
IECLR
IELTG
ITRPL
that has the highest priority
Interrupt Enable And Mask register 16-bit regis-
ter
2 9 4 Usage Recommendations
1 Initialization
Enables each interrupt individually
The recommended initialization sequence is
The bits of IENAM correspond to interrupts 0 –
a Initialize the INTBASE register of the CPU
15 Each bit is encoded as follows
b Program the interrupts’ triggering mode and polarity
0 Interrupt is disabled
1 Interrupt is enabled
Interrupt Pending register Read only 16-bit reg-
ister
Indicates which interrupts are pending Bits 0 –
15 of IPND correspond to interrupts 0–15 Each
bit is encoded as follows
te ^{0 Interrupt is not pending}
1 Interrupt is pending
Edge Interrupt Clear register Write only 16-bit
register
Used to clear pending edge-triggered inter-
rupts Writing to the bit positions of level-trig-
gered interrupts has no effect The bits of IECLR
le ^{correspond to interrupts 0–15 Each bit is en-}
coded as follows
0 No effect
1 Clear the pending interrupt
Edge Level Trigger 16-bit register
Each bit defines the way that the corresponding
o ^{interrupt request is triggered either edge-sensi-}
tive or level-sensitive
Each IETLG bit is encoded as follows
0 Level-sensitive
s ^{1 Edge-sensitive}
For normal invocation of internal interrupt sourc-
es bits 0 5 6 7 and 8 must be ‘‘0’’ bits 2 3 10
11 12 13 and 14 must be ‘‘1’’
Trigger Polarity ITRPL is a 16-bit register that
b _{controls the triggering polarity ITRPL bits are}
encoded as follows
Level-sensitive trigger type
0 Low level
1 High level
O^{Edge-sensitive trigger type}
c Prepare the interrupt routines of the used interrupts
d Clear the used edge-interrupt
e Set the relevant bits of IENAM
f Enable the CPU interrupt (via the PSR register of the
CPU)
2 Clearing
Clearing an interrupt request before it is serviced may
cause a spurious interrupt (i e the CPU detects an inter-
rupt not reflected by IVCT) The user is advised to clear
interrupt requests only when interrupts are disabled
Changing triggering mode or polarity may also cause a
spurious interrupt and should thus be carried out only
when the interrupts are disabled
Clearing any of the IENAM bits should be carried out
while the I bit in the PSR register of the CPU is cleared
3 Nesting
There is no hardware limitation on nesting of interrupts
Interrupts’ nesting is controlled by writing into the Enable
And Mask register (IENAM) When the CPU acknowledg-
es an interrupt the CPU’s PSR I bit is cleared to ‘‘0’’
thus disabling interrupts While an interrupt is in service
the user may allow other interrupts to occur by updating
IENAM then setting PSR I bit to ‘‘1’’ The IENAM register
can be used to control which of the other interrupts is
enabled
2 10 PORTS MODULE
2 10 1 Features
Y _{Individual or group enable set clear of any output port}
Y _{Read latched state of input ports}
Y _{Some Port I O pins can be allocated to other modules}
Y _{External extension output port support}
2 10 2 Operation
This module includes three types of ports
General-purpose input output ports
External output port extension
0 Falling edge
Stepper-motors output ports
1 Rising edge
For normal invocation of internal interrupt sourc-
es bits 0 2 3 5 6 7 8 10 11 12 13 and 14
must be ‘‘1’’
2 10 2 1 General Purpose Input Output Ports
These ports enable access to individual general-purpose
input output pins There are three general purpose ports
Port A provides four input pins Port B provides 12 output
pins Port C provides eight I O pins Some pins are shared
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