NS32FV100 Datasheet, PDF (76/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

4 0 Device Specifications (Continued)
4 6 2 Timing Tables (Continued)
4 6 2 1 Output Signals Internal Propagation Delays (Continued)
Symbol Figure
Description
Reference
Condition
NS32FX200-15
Min
Max
NS32FX200-20
Min
Max
NS32FX200-25
Min
Max
Units
t_UTXDa
4-24 UTXD Signal
Active
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
t_UTXDia
4-24 UTXD Signal
Inactive
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
t_URENa
4-24 UREN Signal
Active
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
t_URENia
4-24 UREN Signal
Inactive
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
t_MWSOa
4-25 MWSO Signal
Active (Note 1)
After R E
CTTL
24
22
20
ns
t_MWSOia
4-25
MWSO Signal
Inactive (Note 1)
After R E
CTTL
24
22
20
ns
t_PIOa
4-26 PIO0–1 Signal
Active
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
te ^tPIOia
4-26 PIO0–1 Signal
Inactive
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 24
a 22
a 20
t_SNHa
4-23 SNH Signal
Active
After R E
CTTL
24
22
20
ns
le ^tSNHia
4-23 SNH Signal
Inactive
After R E
CTTL
24
22
20
ns
t_SBYPSa
4-23
SBYPS Signal
Active
After R E
CTTL
24
22
20
ns
t_SBYPSia 4-23 SBYPS Signal
Inactive
After R E
CTTL
24
22
20
ns
t_ALf
4-17 AD0–AD15 Floating After R E
o _{(Note 4)}
CTTL Ti
15
14
13
ns
t_AHf
4-17 A16–A23 Floating After R E
(Notes 3 4)
CTTL Ti
t_{CTp 2}
t_{CTp 2}
t_{CTp 2}
ns
s tADSf
4-17 ADS Signal Floating After R E
(Notes 3 4)
CTTL Ti
t_{CTp 2}
t_{CTp 2}
t_{CTp 2}
ns
t_DDINf
4-17 DDIN Signal
After R E
Floating (Notes 3 4) CTTL Ti
t_{CTp 2}
t_{CTp 2}
t_{CTp 2}
ns
b t_PCf
4-26 All Port B C Outputs After R E
Floating (Notes 2 4) CTTL
0
t_{CTp 2}
0
t_{CTp 2}
0
t_{CTp 2}
ns
a 15
a 14
a 13
Note 1 When configured as MWIRE signal MWSO is changed on the first CTTL R E following the relevant MWSK edge
Note 2 SNH PCLK UTXD UREN MWSO PIO0–1 SBYPS
Note 3 Float according to HLDA input
O ^{Note 4 The parameters related to the ‘‘floating not floating’’ conditions are guaranteed by characterization Due to tester conditions these parameters are not}
100% tested
75