NS32FV100 Datasheet, PDF (72/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

4 0 Device Specifications (Continued)
4 6 2 Timing Tables
4 6 2 1 Output Signals Internal Propagation Delays
Symbol Figure
Description
Reference
Condition
NS32FX200 – 15
Min
Max
NS32FX200 – 20
Min
Max
NS32FX200-25
Min
Max
Units
t_CLKp
4-8 CCLK Clock Period R E CCLK to
33
500
25
500
20
500
ns
next R E CCLK
t_CLKh
4-8 CCLK High Time
At 3 8V
(Both Edges)
t_{CLKp 2}
b 5 ns
t_{CLKP 2}
b 4 ns
t_{CLKp 2}
b 3 ns
t_CLKl
4-8 CCLK Low Time
At 1 0V
(Both Edges)
t_{CLKp 2}
b 5 ns
t_{CLKP 2}
b 4 ns
t_{CLKp 2}
b 3 ns
t_CWa
4-9 CWAIT Signal Active After R E
CTTL
40
30
24
ns
t_CWia
4-9 CWAIT Signal
Inactive
After R E
CTTL
40
30
24
ns
t_ADSOa
4-16
ADS Signal Active
(Notes 2 5)
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CT p 2} t_{CTp 2}
ns
a 3 a 27 a 3 a 25 a 3 a 23
t_ADSOia
4-16
ADS Signal
Inactive
After R E
CTTL
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CT p 2} t_{CTp 2}
ns
a27
a25
a23
te ^tDDINv
4-16
DDIN Signal
Valid
Before F E
CTTL T1
17
16
12
ns
t_DDINh
4-16 DDIN Signal
After F E
0
0
0
ns
Hold
CTTL T4
le ^tHOLDa
4-16
HOLD Signal
Active
After R E
CTTL
23
21
18
ns
t_HOLDia
4-16
HOLD Signal
Inactive
After R E
CTTL
23
21
18
ns
t_MAv
4-9 MA1–15 Valid
(Note 3)
After R E
CTTL T1
50
36
34
ns
o ^tMACv
4-9 MA1–15 Valid
Column Address
After R E
CTTL T2
60
45
40
ns
t_MAh
4-9 MA1–15 Hold
After R E
t_{CTp 2}
t_{CTp 2}
t_{CTp 2}
ns
CTTL T2 or T4 a 0 ns
a 0 ns
a 0 ns
s tRAh
4-9 MA1–15 Hold
After F E
25
18
14
ns
(Notes 4 5)
RAS
t_ADv
4-17 AD0–15 Valid
(Data) (Note 1)
After R E
CTTL T2
t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2} t_{CTp 2}
ns
a 25
a 20
a 20
b t_ADs
4-17 AD0–15 Setup
Before R E
40
30
18
ns
(Data) (Note 5)
WE0 – 1
t_ADh
4-17
AD0–15 Hold
(Data)
After R E
CTTL T4
t_{CTP 2}
t_{CTP 2}
t_{CTP 2}
ns
O ^{Note 1 tCASa–tADv t 7 ns Guaranteed by design}
Note 2 t_CTp is the first parameter on the input signal list
Note 3 Generated asynchronous to CTTL as a function of the inputs AD0–15 A16–23 and ADS
Note 4 Assuming MA1–15 load l RAS load
Note 5 Guaranteed by characterization Due to tester conditions these parameters are not 100% tested
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