NS32FV100 Datasheet, PDF (74/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

4 0 Device Specifications (Continued)
4 6 2 Timing Tables (Continued)
4 6 2 1 Output Signals Internal Propagation Delays (Continued)
Symbol Figure
Description
Reference
Condition
NS32FX200-15 NS32FX200-20 NS32FX200-25
Units
Min Max Min Max Min Max
t_RASBBa 4-15 RAS0 – 1 Signal Active After R E SOSCI
100
100
100
ns
(Freeze Mode)
at 3 8V
t_RASBBia 4-15 RAS0 – 1 Signal Active After R E SOSCI
100
100
100
ns
(Freeze Mode)
at 3 8V
t_CASBBa
4-15 CAS Signal Active
After R E SOSCI
100
100
100
ns
(Freeze Mode)
at 3 8V
t_CASBBia 4-15 CAS Signal Active
After R E SOSCI
100
100
100
ns
(Freeze Mode)
at 3 8V
t_SDOUTv 4-19 SDOUT Signal Valid After R E CTTL
14
13
12
ns
t_SDOUTh 4-19 SDOUT Signal Hold
After R E CTTL
0
0
0
ns
t_SDFDBKv 4-19 SDFDBK Signal Valid After R E CTTL
14
13
12
ns
t_SDFDBKh 4-19 SDFDBK Signal Hold After R E CTTL
0
0
0
ns
te ^tSCVOv
4-27 SCVO Signal Valid
(Note 1)
After Input
Change
300
300
300
ns
t_SPDWa
4-23 SPDW Signal
Active
After R E
CTTL
24
22
20
ns
t_SPDWia
4-23 SPDW Signal
Inactive
After R E
CTTL
24
22
20
ns
le ^tSDISa
4-23 SDIS Signal
Active
After R E
CTTL
24
22
20
ns
t_SDISia
4-23 SDIS Signal
Inactive
After R E
CTTL
24
22
20
ns
t_SLSa
4-23 SLS Signal
Active
After R E
CTTL
24
22
20
ns
o t_SLSia
4-23 SLS Signal
Inactive
After R E
CTTL
24
22
20
ns
t_SCLK1a
4-23 SCLK1 Signal
Active
After R E
CTTL
24
22
20
ns
s _tSCLK1ia
4-23 SCLK1 Signal
Inactive
After R E
CTTL
24
22
20
ns
t_SCLK2a
4-23 SCLK2 Signal
Active
After R E
CTTL
24
22
20
ns
b _tSCLK2ia
4-23 SCLK2 Signal
Inactive
After R E
CTTL
24
22
20
ns
Note 1 Input change in either Digital input L E of SNH Cycle
O^{Analog input SVI measured at 30 pF}
73