NS32FV100 Datasheet, PDF (6/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

List of Figures (Continued)
FIGURE 4-1 Connection Diagram Top View
66
FIGURE 4-2 Analog Circuitry Block Diagram
69
FIGURE 4-3 TTL Output Signals Specification Standard
70
FIGURE 4-4 TTL Input Signals Specification Standard
70
FIGURE 4-5 CMOS Output Signals Specification Standard
70
FIGURE 4-6 CMOS Input Signals Specification Standard
70
FIGURE 4-7 Input Hysteresis
70
FIGURE 4-8 Clock Waveforms
79
FIGURE 4-9 DRAM Read Bus Cycle
79
FIGURE 4-10 DRAM Write Bus Cycle
80
FIGURE 4-11 ROM SRAM Read Bus Cycle
81
FIGURE 4-12 ROM SRAM Write Bus Cycle (One Wait State)
82
FIGURE 4-13 I O Read Bus Cycle
83
FIGURE 4-14 I O Write Bus Cycle
83
FIGURE 4-15 DRAM Refresh Bus Cycles
84
FIGURE 4-16 DMA Read Transaction (DIR e 0)
85
FIGURE 4-17 DMA Write Transaction (DIR e 1)
86
FIGURE 4-18 Interrupt Signals Timing
87
FIGURE 4-19 Sigma-Delta Signals Timing
87
te ^{FIGURE 4-20 SBYPS Input Signal Timing}
87
FIGURE 4-21 Printer Signals Timing
88
FIGURE 4-22 Reset Signals Timing
88
FIGURE 4-23 Scanner Signals Timing
89
FIGURE 4-24 UART Signals Timing
90
FIGURE 4-25 MWIRE Signals Timing
90
le ^{FIGURE 4-26 Ports Signals Timing}
91
FIGURE 4-27 Analog Signals Timing
91
List of Tables
TABLE 2-1 CTTL MCLON and MCLOFF Values
12
o _{TABLE 2-2 Component Values}
15
TABLE 2-3 Interrupt Sources and Priority Levels
40
TABLE 2-4 DRAM Address Multiplexing
46
s ^{TABLE 2-5 DRAM Address Sizes}
46
TABLE 3-1 R C and L Values
53
TABLE 3-2 System Chip Operation Modes and Power Consumption
53
TABLE A-1 Transmitter Performance
92
Ob ^{TABLE A-2 Receiver Performance}
93
5