NS32FV100 Datasheet, PDF (20/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

2 0 Architecture (Continued)
2 4 2 1 Scanner Signals Generator Block
This block generates the timing control signals required by
CIS and CCD scanners Scanners with line scan time of
2 5 ms 5 ms 10 ms or 20 ms are supported This period is
derived from the TCU module’s time-slots (generated by the
TCU dividing each 20 ms into 256 time-slots)
The block generates the following signals
Scanner Period Pulse (SPP) an internal synchronization
pulse
Scanner Pixel Clock (SPCLK) an internal pixel clock (its
frequency is twice the scanner clock)
Pixel clocks (two phases SCLK1 and SCLK2)
Integrator Discharge Pulse (SDIS)
Scan Line Synchronization Pulse (SLS) Indicates the
beginning of a scan line
Scanner Comparator Preset an internal initialization sig-
nal for the on-chip analog comparator
Active window an internal time frame that controls the
operation of the bitmap generator
Peak Detector Window (SPDW) One of the Automatic
Background Control (ABC) control signals
Scanner interrupt pulse
Scanner motor interrupt pulse
Each signal is generated by an independently programmed
waveform generator The flexible waveform definition facili-
tates the support of different scanner models
Sample and Hold control clock (SNH) Used to sample
the scanner analog video signal
Obsolete ^{FIGURE2-6 BlockDiagramofScanner’sSignalsGeneratorBlock}
TL EE 11331 – 11
19