NS32FV100 Datasheet, PDF (36/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

2 0 Architecture (Continued)
solete ^{FIGURE2-18 DMAI OtoMemoryWriteTransaction(DIR e 1 NFBY e 1)}
TL EE 11331 – 23
The maximum throughput of a DMA channel is 3 125 Mbyte sec (One byte can be transferred at a rate of eight CTTL cycles per
transfer up to 25 MHz )
Note 1 Memory control signals (like CWAIT select and write enable) are generated according to the specifications of the accessed zone
Note 2 The NS32FX100 does not drive data onto AD0–15 till the end of T4 in memory
I O transactions (like NS32FX100 register read transactions)
Ob ^{v Note 3 A in the figure indicates DMA priority resolving points}
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