NS32FV100 Datasheet, PDF (49/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

2 0 Architecture (Continued)
IDLE1 Zone 1 SRAM idle control See IDLEi below
Unpredictable results may occur when
WAIT2
IDLE2
Zone 2 DRAM wait state control See WAITi
below
Zone 2 DRAM idle control See IDLEi below
1 Registers are not accessed according to the above rules
2 Access is made to other locations within the NS32FX100
address space
WAITi
Number of T3W (wait) extension cycles (i e 0 1
2)
000 Seven wait states 100 Three wait states
001 Six wait states
101 Two wait states
010 Five wait states 110 One wait states
011 Four wait states 111 Zero wait states
Note
Some instructions like SBITW and CBITW issue byte transactions
Take care not to use these instructions if they are likely to cause
transactions that violate the rules specified in this section When a
register includes a reserved bit (indicated by ‘‘res’’ field) it must be
written as 0 and its value is undefined when read Bit 6 of MCFG
(marked as reserved) should be written as ‘‘1’’ where specifically
indicated in this document
2 12 2 NS32FX200 NS32FV100 and NS32FX100
Registers
IDLEi
(i e 0 1 2)
0 No idle cycles after the respective transaction
MCFG
rw _l FE0A00
1 Forces two idle cycles after the respective
transaction
te ^WAIT3
Zone 3 I O wait state control
000 Sixteen read waits eighteen write waits
001 Fourteen read waits sixteen write waits
010 Twelve read waits fourteen write waits
011 Ten read waits twelve write waits
100 Eight read waits ten write waits
101 Six read waits eight write waits
110 Four read waits six write waits
111 Two read waits four write waits
WAITR Wait states for DRAM refresh transaction
le ^{0 Three wait states}
1 Zero wait states
Upon reset MWAIT is cleared to ‘‘0’’
2 11 4 Usage Recommendations
Before accessing the DRAM for the first time
a Initialize the Refresh Rate Control (RFRT) register in the
o TCU
b Set Refresh Enabled (RFEN) on
c Initialize BMCFG
d Initialize MWAIT
s e Ensure that you provide an appropriate delay time for
components which require a delay between power-up
and the first DRAM access
2 12 REGISTER SUMMARY
b _{2 12 1 NS32FX100 Registers Access Method}
Registers’ address and access are listed in Section 2 12 2
A byte transaction must be issued to access a byte register
A word-aligned transaction must be issued to access a dou-
ble-word register
O ^{Unless otherwise specified all registers are readable and}
15
res
65
4
3
2
1
0
ESDC EDMA0 ESCAN EPBMS ETPHB ECOUNT
TCU
CSCL
w _l FE0401
7
5
4
3
0
res
F
res
TIMER
rw _l FE0402
15
0
TIMER
l ^{BUZCFG rw FE0405}
7
65
0
BCTRL
res
BUZSWC w _l FE0406
15
0
BUZSWC
TSL
r _l FE0408
7
0
TSL
WDC
rw _l FE040A
7
0
WDC
MCLON w _l FE040C
7
0
MCLON
MCLOFF w _l FE040E
writable
7
0
Unless otherwise specified all contents of the registers are
undefined after reset
MCLOFF
48