NS32FV100 Datasheet, PDF (27/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

2 0 Architecture (Continued)
Strobes Generator
Strobing pulses are generated on the STB0 – 3 output pins if
A train of strobes consists of two or four strobes depending
on the strobes mode The train of strobe pulses starts on
the time slot pre-defined in the Printer Strobes-Start Time
Slot (PSTSL) register The train of strobe pulses starts with
a strobe-on interval followed by a sequence of strobe-off
enabled by the STBEN bit of the Thermal Print-Head Con-
trol (TPHC) register After the last strobe-on interval is com-
pleted the STBEN bit is automatically cleared by hardware
To prevent losing strobe pulses the software should verify
that the bit is cleared before setting it to ‘‘1’’
and strobe-on intervals The duration of the strobe-on inter-
The strobing mode defines both the number of strobes in a
val is controlled by the STBON register and the duration of
train and the distribution of strobes among the STB0 – 3
the strobe-off interval is controlled by the STBOFF register
pins Two strobing modes are supported Two-Strobes
The strobe-on and strobe-off intervals may be programmed
mode and Four-Strobes mode The Strobe Mode (STBM)
while the strobe pulses are being generated After the last
field of the TPHC register selects the strobing mode to be
strobe-on interval is completed a Strobes-Done interrupt
used
pulse is generated The interrupt is periodic occurring when
the pre-defined time slot is reached and the train of strobe
pulses is completed
The two strobing modes are shown in Figure 2-12 and Fig-
ure 2-13 for TPHC SPOLe1 Note that ‘‘Start’’ is the begin-
ning of the time slot and ‘‘Done’’ is the Strobes-Done event
lete ^{FIGURE2-12 FourStrobesMode(STBM e 00)}
TL EE 11331 – 17
Obso ^{FIGURE2-13 TwoStrobesMode(STBM e 01)}
TL EE 11331 – 18
26