NS32FV100 Datasheet, PDF (64/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

4 0 Device Specifications (Continued)
4 1 3 Output Signals
Signal
BUZCLK
CAS
CCLK
CWAIT
DMAK1
DMAK3
FOSCO
HOLD
INTR
MA1 – 15
MWSK
OE
PDO
PEXT
PMPH0 – 3
RAS0
RAS1
SCLK1
SCLK2 DMAK0
SCVO
SDFDBK
Pin Numbers
Description
59
Buzzer Clock Programmable frequency clock for the buzzer
104
DRAM Column Address Strobe Column address strobe for DRAM banks refresh
(NS32FX200 and NS32FV100 )
39
CPU Double Clock Feeds CPU’S OSCIN Asynchronous
103
Continuous Wait Low extends the memory cycle of the CPU
28
DMA Acknowledge Output for DMA channel 1 acknowledge or general purpose
output pin
26
DMA Acknowledge Output for DMA channel 3 acknowledge or general purpose
output pin
37
High-Speed Oscillator Out Asynchronous This line is used as the return path for
the crystal (if used)
115
Hold Request When low HOLD requests the bus from the CPU to perform DMA
operations or to insert idle bus cycles
44
Interrupt Request Low indicates that an interrupt request is being output to the CPU
101 100 99 Memory Address Bus Multiplexed DRAM address (NS32FX200 and NS32FV100 )
98 97 95
te ^{94 93 92}
91 89 88
87 86 85
24
MICROWIRE Shift Clock Output or general purpose output pin
111
Output Enable Used by the addressed device to gate the data onto the data bus
16
Printer Bitmap Shifter Data Output from the bitmap shifter
le ⁶⁵
External Expansion Port Latch Enable
74 73 72 Printer Motor Phases Four phase signals for driving the printer motor
71
106
DRAM Row Address Strobes Row address strobe for DRAM banks 0 and 1
(NS32FX200 and NS32FV100 )
o 105
22
Scanner Clock 1 Output pixel clock or general purpose output pin
29
Scanner Clock 2 Output pixel clock or DMA Acknowledge output for DMA channel
s^{0 acknowledge or general purpose output pin}
79
Scanner Compensated Video Out Analog current for use by ABC or optional video
enhancement circuit
18
Sigma-Delta Feedback Feedback input to the SDC analog receiver Asynchronous
Ob^{output signal}
63