NS32FV100 Datasheet, PDF (23/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

2 0 Architecture (Continued)
Video DAC (Shading-Compensation)
cess on SNH leading edge loads the value of the accessed
The shading-compensation circuit includes an 8-bit multiply-
ing Digital-to-Analog Converter (DAC) that multiplies SVI
the analog input from an external video sample and hold
circuit with a digital reference value (white line) fetched by
DMA channel 0 The Video DAC compensates for the input
offset according to the compensation value in the SVDB
register and the control bits in the SVHC register By writing
to the SVDB register it is possible to control the Video DAC
byte to the DAC’s input Hardware access can take place
only during active video window Software access is carried
out via the SDITH register Software may not access the
buffer during active video window The dither cyclic buffer is
shown in Figure 2-10 For a gray-level image ABC should
be disabled by externally clamping the SBG input to a con-
stant source For this purpose an external analog switch
controlled by any of the Ports module may be used
directly by software In this case the same 8-bit value repli-
ca should be written to both bytes of the register When the
compensation value is greater than the input video signal
Note Eight dither registers are available on all system chips The difference
between the number of supported gray levels lies in the different
characteristics of the associated analog circuits
the compensated video data signal is ‘‘0’’ The compensat-
ed video data at the output of the video DAC feeds the
video comparator It also goes to an external pin (SCVO) to
enable external implementation of an Automatic Back-
ground Control (ABC) circuit
To enable a longer latency for DMA channel 0 operations a
double buffer is used DMA cycles are synchronized to the
leading edge of SNH during active video window
When DMA channel 0 is disabled the same value should be
written to both bytes of the Scanner Video DAC Buffer
(SVDB) register
te ^{2 4 2 4 Threshold DAC (Dithering and Automatic}
Background Control)
The dithering circuit includes an 8-bit multiplying DAC that
multiplies SBG the input from an external Automatic Back-
ground Control (ABC) circuit with the digital dither value
from one of the eight dither bytes The threshold DAC has
no output pin and no I_OFF internal offset current but is
le ^{otherwise similar to the video DAC}
The block includes a cyclic buffer for 64 grey levels The
cyclic buffer contains eight bytes only one of which is ac-
cessible at any given time Any buffer access (software
read software write or hardware read) causes a cyclic shift
Obso ^{in the buffer after the access is completed A hardware ac-}
TL EE 11331 – 15
FIGURE 2-10 Dither Cyclic Buffer
Video Comparator
The output of the shading-compensation (video) DAC is
compared by the video comparator with the output of the
dithering (threshold) DAC The comparator feeds the pixel
generator
Bitmap Accumulator
The bitmap accumulator includes a pixel generator and a
bitmap shift register It uses DMA channel 2 to store the
bitmap into memory
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