NS32FV100 Datasheet, PDF (5/96 Pages) Texas Instruments – NS32FX100 NS32FV100 NS32FX200 System Controller

List of Figures
FIGURE 1-1
FIGURE 1-2
FIGURE 1-3
FIGURE 1-4
FIGURE 1-5
FIGURE 2-1
FIGURE 2-2
FIGURE 2-3
FIGURE 2-4
FIGURE 2-5
FIGURE 2-6
FIGURE 2-7
FIGURE 2-8
FIGURE 2-9
FIGURE 2-10
FIGURE 2-11
FIGURE 2-12
FIGURE 2-13
FIGURE 2-14
FIGURE 2-15
FIGURE 2-16
FIGURE 2-17
FIGURE 2-18
FIGURE 2-19
FIGURE 2-20
FIGURE 2-21
FIGURE 2-22
FIGURE 2-23
FIGURE 2-24
FIGURE 2-25
FIGURE 2-26
FIGURE 3-1
FIGURE 3-2
FIGURE 3-3
FIGURE 3-4
FIGURE 3-5
FIGURE 3-6
FIGURE 3-7
FIGURE 3-8
FIGURE 3-9
FIGURE 3-10
FIGURE 3-11
FIGURE 3-12
FIGURE 3-13
FIGURE 3-14
FIGURE 3-15
FIGURE 3-16
FIGURE 3-17
FIGURE 3-18
FIGURE 3-19
FIGURE 3-20
A FAX Controller Block Diagram
1
NS32FX100 Module Diagram
7
NS32FV100 Module Diagram
7
NS32FX200 Module Diagram
7
System Chip States and Operation Modes
9
Clocks and Traps Connectivity
10
High Speed Oscillator Clocks
11
Low Speed Oscillator Clocks
11
Sigma-Delta Block Diagram
14
SDC Off-Chip Analog Circuit
16
Block Diagram of Scanner’s Signals Generator Block
19
Scanner Pixel Control Signals
20
Scanner Period Control Signals
21
Block Diagram of Scanner’s Video Handling Block
21
Dither Cyclic Buffer
22
Bitmap Shifter Signals
25
Four Strobes Mode (STBM e 00)
26
Two Strobes Mode (STBM e 01)
26
Temperature ADC
27
te ^{DMA Fly-By Read Transaction (DIRe0 FBYe 0)}
32
DMA Fly-By Write Transaction (DIRe1 FBYe0)
33
DMA Memory to I O Read Transaction (DIRe0 NFBYe1)
34
DMA I O to Memory Write Transaction (DIRe1 NFBYe1)
35
Two Adjacent Fly-By DMA Transactions
36
Character Format
37
le ^{MICROWIRE Transaction (CLKMe0)}
39
MICROWIRE Transaction (CLKMe1)
39
Port A
42
Port B
42
Port C
42
External Output Port Extension
43
o ^{Power and Ground Connections}
53
Oscillator Circuits
53
Zones 0 1 (ROM SRAM) Read Transaction Zero Wait State
54
Zones 0 1 (ROM SRAM) Read Transaction One Wait State
54
s _{Zones 0 1 (ROM SRAM) Write Transaction Zero Wait State}
55
Zones 0 1 (ROM SRAM) Write Transaction One Wait State
55
Zone 2 (DRAM) Refresh Transaction Zero Wait State
56
Zone 2 (DRAM) Refresh Transaction Three Wait States
56
b Freeze Mode Refresh Transaction Waveform
56
Zone 2 (DRAM) Read Transaction Zero Wait State
57
Zones 0 1 Access Delayed by a Refresh Transaction (No Wait)
57
Zone 2 (DRAM) Read Transaction One Wait State
58
Zone 2 (DRAM) Write Transaction Zero Wait State
58
O ^{Zone 2 (DRAM) Write Transaction One Wait State}
59
Zone 3 (I O) Read Transaction Two Wait States
59
Zone 3 (I O) Read Transaction Four Wait States
60
Zone 3 (I O) Write Transaction Four Wait States
60
Zone 3 (I O) Write Transaction Six Wait States
61
CPU DMA Arbitration
61
Spaced Memory Transaction Two Tidles after T4
61
4