LM3S1512_16 Datasheet, PDF (76/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

The Cortex-M3 Processor
– An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.
■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 77 lists the interrupts on the LM3S1512 controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 76 shows as having
configurable priority (see the SYSHNDCTRL register on page 131 and the DIS0 register on page 106).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 82.
Table 2-8. Exception Types
Exception Type
-
Vector
Number
0
Reset
1
Non-Maskable Interrupt
2
(NMI)
Hard Fault
3
Memory Management
4
Bus Fault
5
Usage Fault
-
SVCall
Debug Monitor
-
6
7-10
11
12
13
Priority^a
-
-3 (highest)
-2
-1
programmable^c
programmable^c
programmable^c
-
programmable^c
programmable^c
-
Vector Address or
Offset^b
0x0000.0000
0x0000.0004
0x0000.0008
Activation
Stack top is loaded from the first
entry of the vector table on reset.
Asynchronous
Asynchronous
0x0000.000C
0x0000.0010
0x0000.0014
0x0000.0018
-
0x0000.002C
0x0000.0030
-
-
Synchronous
Synchronous when precise and
asynchronous when imprecise
Synchronous
Reserved
Synchronous
Synchronous
Reserved
76
July 15, 2014
Texas Instruments-Production Data