LM3S1512_16 Datasheet, PDF (559/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Stellaris^® LM3S1512 Microcontroller
Figure 16-1. QEI Block Diagram
PhA
PhB
IDX
Control & Status
QEICTL
QEISTAT
Velocity
Predivider
clk
Quadrature
Encoder _dir
QEILOAD
Velocity Timer
QEITIME
Velocity Accumulator
QEICOUNT
QEISPEED
QEIMAXPOS
Position Integrator
QEIPOS
QEIINTEN
Interrupt Control
QEIRIS
QEIISC
Interrupt
16.2
Signal Description
Table 16-1 on page 559 and Table 16-2 on page 559 list the external signals of the QEI module and
describe the function of each. The QEI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the
possible GPIO pin placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 305) should be set to choose the QEI function. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 281.
Table 16-1. QEI Signals (100LQFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
IDX0
10
I
TTL
QEI module 0 index.
PhA0
11
I
TTL
QEI module 0 phase A.
PhB0
47
I
TTL
QEI module 0 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 16-2. QEI Signals (108BGA)
Pin Name
Pin Number Pin Type Buffer Type^a Description
IDX0
G1
I
TTL
QEI module 0 index.
PhA0
G2
I
TTL
QEI module 0 phase A.
PhB0
M9
I
TTL
QEI module 0 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
July 15, 2014
559
Texas Instruments-Production Data