LM3S1512_16 Datasheet, PDF (16/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Table of Contents
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 114
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 114
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 116
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 117
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 118
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 121
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 122
System Control (SYSCTRL), offset 0xD10 ....................................................................... 124
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 126
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 128
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 129
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 130
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 131
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 135
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 141
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 142
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 143
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 144
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 145
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 147
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 148
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 148
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 148
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 148
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 150
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 150
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 150
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 150
System Control ............................................................................................................................ 166
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 181
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 183
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 184
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 185
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 186
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 187
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 188
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 189
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 193
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 194
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 196
Register 12: Device Identification 1 (DID1), offset 0x004 ..................................................................... 197
Register 13: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 199
Register 14: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 200
Register 15: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 202
Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 204
Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 206
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 208
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 210
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July 15, 2014
Texas Instruments-Production Data