LM3S1512_16 Datasheet, PDF (229/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Stellaris^® LM3S1512 Microcontroller
Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31
30
29
28
27
26
Type RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
15
14
13
12
11
10
reserved
Type RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
25
24
23
reserved
RO
RO
RO
0
0
0
9
8
7
RO
RO
RO
0
0
0
22
21
20
19
18
17
16
ADC
RO
RO
RO
RO
RO
RO
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
HIB
reserved
WDT
reserved
R/W
RO
RO
R/W
RO
RO
RO
0
0
0
0
0
0
0
Bit/Field
31:17
16
15:7
6
5:4
3
2:0
Name
reserved
ADC
reserved
HIB
reserved
WDT
reserved
Type
RO
R/W
RO
R/W
RO
R/W
RO
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC0 Reset Control
Reset control for SAR ADC module 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
HIB Reset Control
Reset control for the Hibernation module.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT Reset Control
Reset control for Watchdog unit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 15, 2014
229
Texas Instruments-Production Data